Questions tagged [cpu-pipelines]

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Which of these devices might speed up processor?

I have test question. Which devices inside processor are used to speed up work indirectly i.e. program isn't executing a code for that device? Possible answers: DRAM | Cache | Pipeline | GPU | ...
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How many RAW dependencies are present in these instructions?

What is the number of RAW dependencies in below set of instructions? I1: R1 = R2 - R3 I2: R2 = R1 + R3 I3: R3 = R1 + R2 I4: R1 = R2 - R2 I can see the following ...
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Deep pipeline - cpu architecture

I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance. While reading about vector instruction, I encountered the term deep ...
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Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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A question about Pipeline Cycle

This is my question, I am so confused with my answer, looking for help! This is my answer: Explanation: At the third instruction, instruction is waiting before ID, thus, no stalling is needed. (it ...
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How to make single cycle processor pipelined?

I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design. I suppose, that I should answer that what should be changed on ...
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Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
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pipeline processor timing charts and total cycles

There are basically 2 things i need to figure out. Timing charts Total cycles for the 3 mips instructions. How does it differ when it is branch taken and branch not taken for a "predict not taken ...
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Computer architecture pipelining

LOOP:LW R1,0(R2) ADDI R1,R1,#1 SW R1,0(R2) ADDI R2,R2,#4 SUB R4,R3,R2 BNEZ R4, LOOP If we want to move an instruction into a ...
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In Tomasulo's algorithm, how do reservation stations recognise which results are directed to them, especially where functional units are pipelined?

I am currently researching instruction level parallelism in CPUs and have come across Tomasulo's algorithm for dynamic scheduling. As I understand it so far, once a functional unit computes a result,...
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
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Confusion in speed up calculation for pipeline architecture

This is an online question I am trying to solve. You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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lw and sw hazards example MIPS

The below example confused me: lw $r0, 4($r0) sw $r0, 4($r0) add $r0, $r0, $r0 Using MIPS 5 stage execution what are the hazards we have 1) without forwarding 2) ...
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Any CPUs using value prediction, dynamic instruction reuse?

There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
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In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
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Why reverse pipeline stages in cycle-level simulator?

In pipeline simulator exercise, it says that: Traversing the stages in backwards order simplifies the instruction flow through the pipeline. Also, in gpgpu-sim source code, the stages are reversed ...
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Case where anti-dependency doesn't need pipeline stalling

While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling. But i couldnt find at example for ...
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Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
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Comparing between single-cycled and Pipelined Processor

In order to ensure my understanding on the concept of pipelining is correct, I did some calculation (see below). Pls share your feedback on my understanding. For a single cycle instruction set, ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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How can I build an dependency table to prevent NOPS

Good morning. At the moment I try to understand pipelining of an MIPS processor. I know that, if I have a piece of Code and one instruction depends on the other, than we maybe could a have problem (...
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From where does the Fetch Unit get its instructions?

In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
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Pipelining and five stage of pipelining

I have a question did I write a good table for next code add r3,r2,47 sw r2,0(r1) lw r1,0(r2) lw r2,100(r1) sw r1,200(r2) sub r3,r5,r6 is this ok? I am not so ...
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Data Hazard in Pipelining

To be precise I am here for RAW hazard. Consider a 5 stage pipeline . In case of $I_4-I_1$ dependency , I am not sure if it is an $RAW$ hazard as $I_4$ does not depends on value of $R_1$ that $...
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Pipeline question

I have this multiple choice question from a computer architecture class, a mips processor executes a program at 10 sec, without pipelining and clock rate 100 MHz. When running the program on a ...
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Branch Prediction question

My question relates to a video I watched on YouTube. The pipeline is a 5-stage pipeline which include fetch, decode, ALU, Mem (data), and Write. It mentions that nothing is fetched until we're sure ...
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187 views

Short pipeline or long pipeline

What is meant by a short pipeline? Does that mean the instructions are split into small number of pieces OR length of a piece is short?
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How is the control unit affected by pipelining? [closed]

Compared to not using instruction pipelining. What is different?
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Difference between delayed branches and out-of-order execution

I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
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How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
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What are the prerequisites for instruction pipelining to work?

When can it be applied? When can it not be used? I get the general idea but not what it takes to make it work.
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Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
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Architecture, microarchitecture and ISA in microprocessor [duplicate]

What is Architecture, microarchitecture and ISA in processor. How do they relate to each other and what is the difference between them. Elucidate their differences with examples so that it is ...
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CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
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Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
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The total time require for a pipeline to execute

The book says that a total time required for a pipeline with k stages to execute n instructions is as follows. $T _{k,n} =[pqnk+(1-pq)(k+n-1)] \tau$ p is the probability of encountering a branch ...
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predication execution, branch prediction

Below is a paragraph from a book. In an ordinary superscalar processor, we would use branch prediction to guess which of the given instructions is to be executed, and go down that path. If the ...
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Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
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How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y R4 = R2 + X ...
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MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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Do unconditional branches cause control hazards?

Do unconditional branches, such as jump/goto instructions cause control hazards? If so, why? I am wondering because if ...
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How can I make a pipeline with undefined/unlimited stages?

I've been told that if you understand a pipeline then you should be able to make it with any depth, but I can only do 4 stages and maybe 5 if the memory is not too slow. How can I learn how to make ...
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Types of pipelining?

if pipelining is devided to polyfunctional pipelining and monofunctional pipelining(im sorry im not a native speaker the name may be incorect) and the polyfunctional pipelining is futher devided to ...
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How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
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Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
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Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
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What is the difference between Data Hazard and Dependencies in Pipelining

In my GATE Exam I have given with the following question statements and R5 ← R0 + R1 R6 ← R2 * R5 R5 ← R3 - R6 R6 ← R5/R4 X ← R6 the question was to calculate number of Output,True and Anti ...
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What is the impact of locality principles on the pipelining techniques?

I know what are both locality principles and pipelining techniques. But I can't see any sort of interconnection between the two things. How can locality principles impact pipelining techniques?
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how long will it take to execute a ten-stage pipeline [duplicate]

Suppose you design a computer with a ten-stage Pipeline to execute one instruction, with each stage taking 5nsec A)how long ...