Questions tagged [cpu-pipelines]
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91
questions
2
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1answer
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Load and Store Data hazard problem in 5-stages pipeline
Hi everyone and first of all thank you for been reading.
I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction.
(Assume that we're working ...
2
votes
1answer
2k views
what are the key advantages of pipelining
I was trying to look my book computer architecture and design, but I can not find the answer for this question.
what are-the key-advantages of pipelining?
0
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0answers
13 views
Double Write After Write Dependency in out-of-order/in-order executions
What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register.
We know we can solve a simple WAW dependency by ...
1
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0answers
44 views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
0
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0answers
16 views
How to compute the Cycles in a pipelined single cycle processor
I'm an undergrad studying computer engineering and I'm in my first of many courses on computer organization/architecture. In the lectures and online I see diagrams like the one pictured below from the ...
-1
votes
1answer
52 views
Calculating the pipeline speed up in case we have an infinite amount of stages
I have the following question:
We begin with a computer implemented in single-cycle implementation.
When the stages are split by functionality, the stages do not require
exactly the same amount of ...
0
votes
1answer
31 views
MIPS pipeline: choosing between slowing down a stage and adding a new stage
Suppose a new, more complicated, instruction is desired for this
simple pipelined MIPS processor. Suppose, also, it could be
implemented by either (a) adding new logic to the execute stage of the
...
0
votes
1answer
74 views
Calculate Stages in Non-Pipelined Processor
I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :-
...
1
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1answer
43 views
How many RAW dependencies are present in these instructions?
What is the number of RAW dependencies in below set of instructions?
I1: R1 = R2 - R3
I2: R2 = R1 + R3
I3: R3 = R1 + R2
I4: R1 = R2 - R2
I can see the following ...
0
votes
0answers
15 views
Why cannot Operand forwarding remove all RAW hazards?
I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
0
votes
2answers
290 views
How to improve the CPI and Speed up factor in CPU-OS simulator?
I am using the CPU-OS simulator by Besim Mustafa(https://www.merlot.org/merlot/viewMaterial.htm?id=476196) and I am studying Pipeline Stages. I have written a simple program and captured the metrics ...
1
vote
0answers
30 views
How can I get 8 bits output from 4 bit CPU?
I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
2
votes
0answers
13 views
Detecting Data and Control Hazards for a mips 5 stage pipeline
I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
-1
votes
1answer
14 views
Neural branch predictors linear, classical predictors exponential, in resources?
Wikipedia states:
The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource ...
0
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0answers
284 views
Deep pipeline - cpu architecture
I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance.
While reading about vector instruction, I encountered the term deep ...
0
votes
2answers
75 views
How to make single cycle processor pipelined?
I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design.
I suppose, that I should answer that what should be changed on ...
0
votes
2answers
419 views
Computer architecture pipelining
LOOP:LW R1,0(R2)
ADDI R1,R1,#1
SW R1,0(R2)
ADDI R2,R2,#4
SUB R4,R3,R2
BNEZ R4, LOOP
If we want to move an instruction into a ...
3
votes
2answers
253 views
How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?
I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together.
If, for example, instructions are meant to be fetched in one stage of ...
-1
votes
2answers
1k views
Confusion in speed up calculation for pipeline architecture
This is an online question I am trying to solve.
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
0
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2answers
3k views
lw and sw hazards example MIPS
The below example confused me:
lw $r0, 4($r0)
sw $r0, 4($r0)
add $r0, $r0, $r0
Using MIPS 5 stage execution what are the hazards we have 1) without forwarding 2) ...
0
votes
1answer
92 views
Any CPUs using value prediction, dynamic instruction reuse?
There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on ...
1
vote
1answer
904 views
In instructions pipelining, why does register read/write take up only half clock cycle?
While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
1
vote
2answers
66 views
Why reverse pipeline stages in cycle-level simulator?
In pipeline simulator exercise, it says that:
Traversing the stages in backwards order simplifies the instruction flow through the pipeline.
Also, in gpgpu-sim source code, the stages are reversed ...
0
votes
1answer
25 views
Case where anti-dependency doesn't need pipeline stalling
While exploring the various types of data hazards in a pipeline, I came across a statement in my book which said that anti-dependency mayn't lead to cycle stalling.
But i couldnt find at example for ...
2
votes
2answers
141 views
Is there a CPU architecture which allows early register access?
In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
1
vote
1answer
33 views
From where does the Fetch Unit get its instructions?
In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
1
vote
1answer
116 views
Data Hazard in Pipelining
To be precise I am here for RAW hazard.
Consider a 5 stage pipeline .
In case of $I_4-I_1$ dependency , I am not sure if it is an $RAW$ hazard as $I_4$ does not depends on value of
$R_1$ that $...
0
votes
1answer
243 views
Pipeline question
I have this multiple choice question from a computer architecture class, a mips processor executes a program at 10 sec, without pipelining and clock rate
100 MHz. When running the program on a ...
0
votes
1answer
82 views
Branch Prediction question
My question relates to a video I watched on YouTube.
The pipeline is a 5-stage pipeline which include fetch, decode, ALU, Mem (data), and Write.
It mentions that nothing is fetched until we're sure ...
1
vote
1answer
369 views
Short pipeline or long pipeline
What is meant by a short pipeline?
Does that mean the instructions are split into small number of pieces OR length of a piece is short?
0
votes
1answer
202 views
How is the control unit affected by pipelining? [closed]
Compared to not using instruction pipelining. What is different?
2
votes
2answers
352 views
Difference between delayed branches and out-of-order execution
I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
2
votes
1answer
292 views
How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:
List item before effective address calculation has started
during effective ...
0
votes
1answer
27 views
What are the prerequisites for instruction pipelining to work?
When can it be applied? When can it not be used? I get the general idea but not what it takes to make it work.
1
vote
0answers
450 views
Pipelining without operand forwarding
I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l)
One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
-4
votes
1answer
2k views
Architecture, microarchitecture and ISA in microprocessor [duplicate]
What is Architecture, microarchitecture and ISA in processor. How do they relate to each other and what is the difference between them.
Elucidate their differences with examples so that it is ...
3
votes
1answer
104 views
CPU pipelining stages
I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
0
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1answer
2k views
Bubble in a pipeline
When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
2
votes
1answer
345 views
The total time require for a pipeline to execute
The book says that a total time required for a pipeline with k stages to execute n instructions is as follows.
$T _{k,n} =[pqnk+(1-pq)(k+n-1)] \tau$
p is the probability of encountering a branch ...
0
votes
2answers
115 views
predication execution, branch prediction
Below is a paragraph from a book.
In an ordinary superscalar processor, we would use branch prediction to guess which of the given instructions is to be executed, and go down that path. If the ...
1
vote
1answer
462 views
Is finding cache size possible with information given?
An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set.
A) What is the size of the cache in bytes?
...
1
vote
1answer
213 views
How to show potential pipeline hazards
Based on following table, I have to show if there is any potential pipeline hazard in the following code segments:
X = R2 + Y
R4 = R2 + X
...
1
vote
0answers
509 views
MIPS Pipeline Hazards - Branch Delay Slot
I'm confused about this exercise.
We have assembly code:
...
1
vote
2answers
2k views
Do unconditional branches cause control hazards?
Do unconditional branches, such as jump/goto instructions cause control hazards? If so, why?
I am wondering because if ...
0
votes
1answer
119 views
How can I make a pipeline with undefined/unlimited stages?
I've been told that if you understand a pipeline then you should be able to make it with any depth, but I can only do 4 stages and maybe 5 if the memory is not too slow. How can I learn how to make ...
0
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0answers
543 views
Types of pipelining?
if pipelining is devided to polyfunctional pipelining and monofunctional pipelining(im sorry im not a native speaker the name may be incorect)
and the polyfunctional pipelining is futher devided to ...
3
votes
1answer
6k views
How are the control signals derived in the MIPS pipeline?
NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
2
votes
0answers
167 views
Why do processor designers allow some pipeline hazards to occure [closed]
Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
2
votes
2answers
74 views
Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?
I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
0
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1answer
4k views
What is the difference between Data Hazard and Dependencies in Pipelining
In my GATE Exam I have given with the following question statements and
R5 ā R0 + R1
R6 ā R2 * R5
R5 ā R3 - R6
R6 ā R5/R4
X ā R6
the question was to calculate number of Output,True and Anti ...
