Questions tagged [cpu-pipelines]

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Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
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MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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1answer
24 views

How many RAW dependencies are present in these instructions?

What is the number of RAW dependencies in below set of instructions? I1: R1 = R2 - R3 I2: R2 = R1 + R3 I3: R3 = R1 + R2 I4: R1 = R2 - R2 I can see the following ...
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Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
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MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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Which of these devices might speed up processor?

I have test question. Which devices inside processor are used to speed up work indirectly i.e. program isn't executing a code for that device? Possible answers: DRAM | Cache | Pipeline | GPU | ...
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61 views

Deep pipeline - cpu architecture

I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance. While reading about vector instruction, I encountered the term deep ...
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42 views

A question about Pipeline Cycle

This is my question, I am so confused with my answer, looking for help! This is my answer: Explanation: At the third instruction, instruction is waiting before ID, thus, no stalling is needed. (it ...
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23 views

pipeline processor timing charts and total cycles

There are basically 2 things i need to figure out. Timing charts Total cycles for the 3 mips instructions. How does it differ when it is branch taken and branch not taken for a "predict not taken ...
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In Tomasulo's algorithm, how do reservation stations recognise which results are directed to them, especially where functional units are pipelined?

I am currently researching instruction level parallelism in CPUs and have come across Tomasulo's algorithm for dynamic scheduling. As I understand it so far, once a functional unit computes a result,...
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1answer
40 views

Calculate Stages in Non-Pipelined Processor

I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :- ...
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Comparing between single-cycled and Pipelined Processor

In order to ensure my understanding on the concept of pipelining is correct, I did some calculation (see below). Pls share your feedback on my understanding. For a single cycle instruction set, ...
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23 views

Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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59 views

How can I build an dependency table to prevent NOPS

Good morning. At the moment I try to understand pipelining of an MIPS processor. I know that, if I have a piece of Code and one instruction depends on the other, than we maybe could a have problem (...
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29 views

Renaming registers

I have this code ...
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28 views

Pipelining and five stage of pipelining

I have a question did I write a good table for next code add r3,r2,47 sw r2,0(r1) lw r1,0(r2) lw r2,100(r1) sw r1,200(r2) sub r3,r5,r6 is this ok? I am not so ...
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494 views

Types of pipelining?

if pipelining is devided to polyfunctional pipelining and monofunctional pipelining(im sorry im not a native speaker the name may be incorect) and the polyfunctional pipelining is futher devided to ...
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50 views

What is the impact of locality principles on the pipelining techniques?

I know what are both locality principles and pipelining techniques. But I can't see any sort of interconnection between the two things. How can locality principles impact pipelining techniques?
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373 views

Pipeline depth with idle stages

To keep througput close to 1/cycle when there is a multi-cycle stage that sends a command to a far module then gets answer(10 clocks per send or receive), could separating it in two(send + receive) ...
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34 views

Do add commands in an pipeline wait for each other's result?

Let be given a 4-step pipeline with the steps "Get command, get operands, Execute command, Write back result" and an Assembler Code: ...
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140 views

What are exceptions and how they will be raised in pipeline

Hi I am not sure what is exception here and how it will be raised in following case Sub $11,$2,$4 And $12,$2,$5 Or $13, $2,$6 Add $1,$2,$1 Slt $15,$6,$7 I was ...