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Questions tagged [cpu-pipelines]

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27
votes
3answers
6k views

What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
11
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2answers
503 views

Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather ...
8
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1answer
2k views

When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different ...
4
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1answer
986 views

Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 … )?

Consider a four stage pipeline, and each stage has delays D1, D2, D3 and D4, so the total delay because of the various stages should be N * (D1 + D2 + D3 + D4) ...
4
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1answer
2k views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...
3
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2answers
176 views

Clear interrupt instruction in a pipelined CPU

Say you execute a clear interrupt instruction (CLI) in a pipelined CPU. While that instruction is being fetched, an interrupt occurs, so the instruction after the CLI is from the interrupt handler. ...
3
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3answers
7k views

Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: <...
3
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2answers
114 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
3
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1answer
91 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
3
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1answer
2k views

Does register renaming remove all kinds of WAR hazard?

For the following two instruction [Note: MOV Destination, Source ] i1 : MOV R1, R2 i2 : ADD R2, R3 Since i1 is reading from R2 and i2 is writing to R2 there is ...
3
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1answer
873 views

Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
3
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1answer
5k views

How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
2
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1answer
131 views

RISC machines have register renaming?

I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming? I know that ...
2
votes
1answer
140 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
2
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1answer
2k views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
2
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2answers
244 views

Difference between delayed branches and out-of-order execution

I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, ...
2
votes
2answers
133 views

Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
2
votes
1answer
887 views

Which hazards are solved by instruction reordering?

I am not clear on whether it's data and control hazards, or control hazards only. Also, the "solved" word confuses me - technically, instruction reordering is used to solve dependences and thus ...
2
votes
2answers
90 views

How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together. If, for example, instructions are meant to be fetched in one stage of ...
2
votes
1answer
256 views

Branch wrong prediction pipeline

Let's say we have a pipeline with 20 stages. If the testing for the jump condition is done at stage 14 and we have a wrong prediction, then the instructions processed in those 14 stages, that shouldn'...
2
votes
1answer
190 views

In instruction pipelining, can we forward an operand more than one clock cycle?

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from ...
2
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1answer
68 views

Identical register input operands in assembly

The question is not specific to any processor. Can I have an assembly instruction, like: ADD R1 R0 R0 R1 is the destination. ...
2
votes
2answers
69 views

Does splitting a process across 4 terminal windows decrease the time it takes?

Basically, I using an algorithm called 'miranda' to look at miRNA targets and it only runs on a single thread. It compares everything in one file against everything in another file, produces a file as ...
2
votes
1answer
224 views

The total time require for a pipeline to execute

The book says that a total time required for a pipeline with k stages to execute n instructions is as follows. $T _{k,n} =[pqnk+(1-pq)(k+n-1)] \tau$ p is the probability of encountering a branch ...
2
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2answers
50 views

Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
2
votes
1answer
8k views

What's the difference between dynamic and static pipelines?

I was trying to understand what a reservation table is in the context of pipelining, when I found this reference here, where the author mentions that there are static and dynamic pipelines. According ...
2
votes
1answer
3k views

Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
2
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1answer
1k views

Read After Write(RAW) hazard

I am confused in finding RAW dependencies whether we have to find only in adjacent instructions or non-adjacent also. consider the following assembly code I1: ADD R1 , R2, R2; I2: ADD R3, R2, R1; ...
2
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1answer
754 views

Load and Store Data hazard problem in 5-stages pipeline

Hi everyone and first of all thank you for been reading. I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction. (Assume that we're working ...
2
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0answers
160 views

Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
2
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0answers
210 views

MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
2
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1answer
40 views

Effective computation on linear data without random access

recently I've started thinking about caching problems in modern CPUs, where they struggle to adequately fetch program data (not instructions) in time, so that it can be computed further. So then I ...
1
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2answers
383 views

For data-path cycles in MIPS, what determines wheter a control signal gets the “don't-care” value?

For example for the sw command in MIPs, the control signal values are ALUOp1: 0 ALUOp: 0 RegWrite: 0 MemRead: x MemWrite: 1 Branch: 0 ALUsrc: 1 RegDest: x MemToReg: x Why do memRead, ...
1
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1answer
29 views

From where does the Fetch Unit get its instructions?

In the ARM Architecture pipelining stages, we know that the instructions pass from fetch to decode and so on? But, from where does the fetch unit get the instructions?
1
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2answers
1k views

Do unconditional branches cause control hazards?

Do unconditional branches, such as jump/goto instructions cause control hazards? If so, why? I am wondering because if ...
1
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1answer
37 views

Can an instruction with a dependency read the register in same cycle as it's being written?

I'm learning about superscalar processors and struggling with it a bit. I wrote an assembly program and now must move it through in-order in-issue completion and I have a question about instructions ...
1
vote
1answer
52 views

Basic question about branches and pipelines

In which stage ( on an ideal 5-stage pipeline ) are branches and hazards handled? How much is the branch penalty for a branch hazard or data hazard. Is there different stages to find data hazards or ...
1
vote
1answer
590 views

pipeline execution time

Lets suppose that 20 percent of the instructions in a program are branch instructions.The static prediction of the jumps supposes that the jumps don't happen. I should find the execution time in two ...
1
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1answer
179 views

Pipelining and Preemption

According to the concepts of Pipelining, In a single cycle different stages of different instructions are executed. Now I have a bit of confusion here, that if a single processing element is ...
1
vote
1answer
813 views

A question from Computer Organization on Peak Clock Frequency

Given below are 3 different pipelined processors: $P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ 2....
1
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1answer
278 views

In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
1
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2answers
45 views

Why reverse pipeline stages in cycle-level simulator?

In pipeline simulator exercise, it says that: Traversing the stages in backwards order simplifies the instruction flow through the pipeline. Also, in gpgpu-sim source code, the stages are reversed ...
1
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1answer
93 views

Data Hazard in Pipelining

To be precise I am here for RAW hazard. Consider a 5 stage pipeline . In case of $I_4-I_1$ dependency , I am not sure if it is an $RAW$ hazard as $I_4$ does not depends on value of $R_1$ that $...
1
vote
1answer
271 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
1
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1answer
186 views

How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y R4 = R2 + X ...
1
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2answers
304 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
1
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2answers
1k views

Calculating speedup for a two-way superscalar cpu

I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows: There is a two-way superscalar CPU with 2 ...
1
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1answer
24 views

How many RAW dependencies are present in these instructions?

What is the number of RAW dependencies in below set of instructions? I1: R1 = R2 - R3 I2: R2 = R1 + R3 I3: R3 = R1 + R2 I4: R1 = R2 - R2 I can see the following ...
1
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0answers
302 views

Pipelining without operand forwarding

I've been doing the HPC course from Udacity (https://classroom.udacity.com/courses/ud007/l) One of the problems is as follows (apologies for the image, as I was unable to format this using $\LaTeX$): ...
1
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0answers
400 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...