Questions tagged [cpu-pipelines]

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Can an instruction with a dependency read the register in same cycle as it's being written?

I'm learning about superscalar processors and struggling with it a bit. I wrote an assembly program and now must move it through in-order in-issue completion and I have a question about instructions ...
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1answer
259 views

Branch wrong prediction pipeline

Let's say we have a pipeline with 20 stages. If the testing for the jump condition is done at stage 14 and we have a wrong prediction, then the instructions processed in those 14 stages, that shouldn'...
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376 views

Pipeline depth with idle stages

To keep througput close to 1/cycle when there is a multi-cycle stage that sends a command to a far module then gets answer(10 clocks per send or receive), could separating it in two(send + receive) ...
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383 views

For data-path cycles in MIPS, what determines wheter a control signal gets the “don't-care” value?

For example for the sw command in MIPs, the control signal values are ALUOp1: 0 ALUOp: 0 RegWrite: 0 MemRead: x MemWrite: 1 Branch: 0 ALUsrc: 1 RegDest: x MemToReg: x Why do memRead, ...
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What is the difference between Data Hazard and Dependencies in Pipelining

In my GATE Exam I have given with the following question statements and R5 ← R0 + R1 R6 ← R2 * R5 R5 ← R3 - R6 R6 ← R5/R4 X ← R6 the question was to calculate number of Output,True and Anti ...
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Computer architecture pipelining

LOOP:LW R1,0(R2) ADDI R1,R1,#1 SW R1,0(R2) ADDI R2,R2,#4 SUB R4,R3,R2 BNEZ R4, LOOP If we want to move an instruction into a ...
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Do add commands in an pipeline wait for each other's result?

Let be given a 4-step pipeline with the steps "Get command, get operands, Execute command, Write back result" and an Assembler Code: ...
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604 views

Question about branch hazards on 4-stage pipeline

Let's say that conditional branches are resolved at the 2nd-stage on a 4-stage pipeline. Why is there different penalties on a taken branch versus an untaken branch ? Should the penalty be the same ...
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1answer
52 views

Basic question about branches and pipelines

In which stage ( on an ideal 5-stage pipeline ) are branches and hazards handled? How much is the branch penalty for a branch hazard or data hazard. Is there different stages to find data hazards or ...
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1answer
132 views

RISC machines have register renaming?

I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming? I know that ...
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1answer
190 views

In instruction pipelining, can we forward an operand more than one clock cycle?

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from ...
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1answer
3k views

Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
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1answer
186 views

How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y R4 = R2 + X ...
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2answers
133 views

Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
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114 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
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What are exceptions and how they will be raised in pipeline

Hi I am not sure what is exception here and how it will be raised in following case Sub $11,$2,$4 And $12,$2,$5 Or $13, $2,$6 Add $1,$2,$1 Slt $15,$6,$7 I was ...
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1answer
1k views

Read After Write(RAW) hazard

I am confused in finding RAW dependencies whether we have to find only in adjacent instructions or non-adjacent also. consider the following assembly code I1: ADD R1 , R2, R2; I2: ADD R3, R2, R1; ...
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Clear interrupt instruction in a pipelined CPU

Say you execute a clear interrupt instruction (CLI) in a pipelined CPU. While that instruction is being fetched, an interrupt occurs, so the instruction after the CLI is from the interrupt handler. ...
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595 views

pipeline execution time

Lets suppose that 20 percent of the instructions in a program are branch instructions.The static prediction of the jumps supposes that the jumps don't happen. I should find the execution time in two ...
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1answer
180 views

Pipelining and Preemption

According to the concepts of Pipelining, In a single cycle different stages of different instructions are executed. Now I have a bit of confusion here, that if a single processing element is ...
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2k views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
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2k views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...
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1answer
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Identical register input operands in assembly

The question is not specific to any processor. Can I have an assembly instruction, like: ADD R1 R0 R0 R1 is the destination. ...
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1answer
2k views

Does register renaming remove all kinds of WAR hazard?

For the following two instruction [Note: MOV Destination, Source ] i1 : MOV R1, R2 i2 : ADD R2, R3 Since i1 is reading from R2 and i2 is writing to R2 there is ...
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986 views

Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 … )?

Consider a four stage pipeline, and each stage has delays D1, D2, D3 and D4, so the total delay because of the various stages should be N * (D1 + D2 + D3 + D4) ...
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1answer
888 views

Which hazards are solved by instruction reordering?

I am not clear on whether it's data and control hazards, or control hazards only. Also, the "solved" word confuses me - technically, instruction reordering is used to solve dependences and thus ...
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MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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305 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
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What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
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Calculating speedup for a two-way superscalar cpu

I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows: There is a two-way superscalar CPU with 2 ...
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1answer
40 views

Effective computation on linear data without random access

recently I've started thinking about caching problems in modern CPUs, where they struggle to adequately fetch program data (not instructions) in time, so that it can be computed further. So then I ...
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Difference in CPU Wattage Question [closed]

If I have 2 CPU's of the same manufacturer... say AMD Both are Quad-Core, Both are rated at 3.6Ghz 1 is 100W, the other is 65W Will the one with the higher wattage out-perform the lower one and why?...
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Does splitting a process across 4 terminal windows decrease the time it takes?

Basically, I using an algorithm called 'miranda' to look at miRNA targets and it only runs on a single thread. It compares everything in one file against everything in another file, produces a file as ...
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814 views

A question from Computer Organization on Peak Clock Frequency

Given below are 3 different pipelined processors: $P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ 2....
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874 views

Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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3answers
8k views

Execution time of an uneven pipeline

I was trying to solve a question dealing with n instructions in an uneven pipeline with k stages. I came across a generic formula for even pipelines i.e. (k + n - 1) * clock cycle. But I feel this ...
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1answer
5k views

How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
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3answers
7k views

Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: <...
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1answer
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When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different ...
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505 views

Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather ...