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Questions tagged [cpu]

CPU, stands for Central Processing Unit. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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Supercomputers have millions of CPUs or cores. Is there a central chip or CPU that controls all the cores?

What device integrates and coordinates all the data from millions of CPUs/cores in a supercomputer? To call these cores CPUs (Central Processing Unit) seems wrong when they are not central at all but ...
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CPU utilization estimation

In the Modern Operating System by Andrew Tanenbaum, Herbert Bos the authors provide their explanation of the concept of CPU utilization in the following way: A better model is to look at CPU usage ...
Ilya Loskutov's user avatar
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
Abhishek Ghosh's user avatar
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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How to prove a given sequence of x86 instructions is shortest possible?

Say we want to find a shortest possible sequence of x86 instructions to move the $9^{th} - 16^{th}$ bit of the $eax$ register to the $24^{th} - 31^{th}$ bit of the $ebx$ register without changing the ...
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Where does the CPU scheduler sit in a layered OS design

In a layered approach to OS design, each layer can only access routines from the layers below itself. For example, say I had two levels: memory management and the CPU scheduler Where does the CPU ...
ethane's user avatar
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CISC, RISC and anything else?

Is there a processor architecture that falls outside the CISC and RISC categories? I'm vaguely familiar with RISC and CISC; my research thus far indicates that either a processor is RISC or CISC, ...
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How is the size of a register related to the size of primary memory?

I understand that registers are temporary storage compartments which (usually) hold 8 bits, or 1 byte, of information at a time. This information is sent from a register into the Central Processing ...
Valentine's user avatar
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How does the Spark M7 “Concurrent Fine-grain Memory Migration” benefit a garbage collector?

Sun has been making a lot of noise about the Spark M7 and its inbuilt support for the java garbage collector. However there seem to be very little easy to find information about it. Please can ...
Ian Ringrose's user avatar
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Can compilers improve performance in real workloads by inserting prefetches in their output?

Prefetching is a task that the compiler feels like it should be suited for. Prefetching requires knowing in advance what data the program is about to load, and the compiler has a ton of information at ...
Narrateur du chaos's user avatar
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How a processor scales in terms of components

I'm still very early in understanding some computer science basics. I find it easiest to learn things when I have some oversight of what I can expect. Is there any trend to the number of logical gates ...
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
Magnus's user avatar
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How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
sttc1888's user avatar
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Where is the register position in a CPU (real image illustration)?

I hear that register is in CPU, but the CPU iamge I generally see doesn't mark the position of register, can anyone provide a ...
yu yang Jian's user avatar
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Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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Does each assembly language correspond to one instruction-set-architecture?

This is a quote from wikipedia: Each computer architecture has its own machine language. Computers differ in the number and type of operations they support, in the different sizes and numbers of ...
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Is the longest datapath really the limiting factor on clock cycle speed?

I've been watching a lecture series on computer organization and one of the lecturers statements is something along the lines of 'the clock cycle can only be as fast as the time it takes to complete ...
Battlefrisk's user avatar
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Little Man Computer Simulator Input Code

I'm just learning about the Little Man Computer CPU simulator, and am using a version online here: http://peterhigginson.co.uk/lmc/ The instruction set used by the simulator is the same as the one ...
Robin Andrews's user avatar
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MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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Processor system synchronization?

Processor has the internal clock which is a multiplier of the main clock which is present on the motherboard which is designed by keeping in mind the critical path and the slowest device on board, ...
Muhammad Usman's user avatar
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How are micro commands processed?

In the lecture we are told about the very basics about CPU. However after the introductory part I found that there are still some things I don't understand too well or which were not really addressed ...
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Is there a delay between two commands to read data from RAM?

Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
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Step in RISC-V program on a Pipelined Processor

I struggle to understand a step in the following solution to a RISC-V exercise. Exercise: a pipelined RISC-V processor with no data forwarding paths executes the following program. For each ...
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Cache Miss in First Private Cache but Hit in Shared LEvel 2 Cache: Does it Result in a Penalty?

In the context of Shared Memory Multiprocessor (SMP) systems with different cache levels, if a cache miss occurs in the first private cache but is followed by a hit in the second shared cache, would ...
First_1st's user avatar
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How to find optimum number of cpu cores for a workload

Following bar graph shows maximum percentage cpu utilization of F16sv2 (16vcpu &32GB) azure virtual machine in last 30 days. Only sometimes CPU usage goes more than 60 percentage. How to find the ...
Amal's user avatar
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Neural networks as building blocks of a computer

I think I have developed a logic circuit which by using combinational logic and flip flops learns to perform the XNOR logic between 2 bits.It is a kind of state machine. Suppose we built a computer ...
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Why do these 8 bit registers use 16 I/O wires for input and output to the bus? Why not use 8 wires for both input and output?

I'm looking at this diagram from Ben Eater's "8 bit computer" tutorial What's the need to use separate 8 wires for only data input, and another 8 wires only for data output? Why not use only ...
Ken Kaneki's user avatar
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Logical circuit for priority resolution in interrupt controllers (with configurable priority, not fixed)

I'm interested in what the typical solution is for priority resolution in interrupt controllers. I assume a hardware logic circuit is used, and not software. For interrupt controllers with fixed ...
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What does the CPU do in AI model training?

I'm new to computing and even newer still to AI model training. However I am wondering the role of the CPU during training of LLM. I'm aware that the CPUs are good for performing strings of ...
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Can a CPU instruction be split into 2 inputs?

Let's say there was a CPU with an input bus of 4 bits and the 4 bits are the opcode then the next 4 bits are the operand. It would just be an 8-bit instruction split in two. Is this possible and how ...
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Dependency in pipeline

Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous ...
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A question about cpu utilization

Here's a question in the OS textbook about calculating the cpu utilization. I've tried to write down the (A) by myself as below. ...
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Do ALUs tend to do operations in parallel even if they are not selected by the machine instruction?

I was playing nandgame.com and noticed that the arithmetic unit of the ALU was doing both the add and subtract operation in parallel, but only asks for one operation per instruction. This to me seemed ...
user52174's user avatar
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Why XMM register width is 128-bit while double precision floating point is 64-bit?

As far as I know, XMM is used to store floating point. But Highest width floating point according IEEE754 standard is double precision (64-bit). But why XMM register width is 128-bit. Is another 64-...
Muhammad Ikhwan Perwira's user avatar
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Superscalar design on SimpleScalar simulation

I've learnt theoretically Computer Architecture at uni.However I can't wrap my head around it in practice. I am using Simple Scalar tool to simulate a benchmark program with configurable computer ...
ankakusu 's user avatar
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Why we need CPU registers with pipeline?

I understand how CPUs work in general in RiscV, but things got a little complicated with pipeline and I don't get it why we need registers at all. For example, let's look at: When the ALU's input was ...
Roy's user avatar
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Alu architecture of a Hack Computer

I'm currently studying the ALU architecture (of a Hack computer) and how it works. As part of my assignments, I have been asked the following question: If we want the ALU to compute the function y-1, ...
Hynisel's user avatar
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What is related to the no of instructions a CPU can handle at one time?

Which of the below choices is related to the number of instructions a CPU can handle at one time? A) 32bit word size B) 3GHz clock speed I think should be (A). 2^32 instruction at one time?
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About clock cycles executed

i have a pretty basic question, but for example a cpu clock at 3ghz, does that mean it can do 3 billion cycles per second, or does it every second always will make since 3 billion cycles?
Aten's user avatar
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Why interrupts can help to increase the efficiency of a user program that contains many I/O operations?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. I get the general mechanisms of how interrupts are handled in computer systems, but the results ...
Sean Zu's user avatar
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What would happen in this priority-based round-robin CPU scheduling algorithm case?

I've been implementing some kind of CPU Scheduling Algorithms in Python. And I am really confused with one of the cases what'd be implemented in this case. Let us assume that the time quantum is 10. ...
erenrock00's user avatar
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Why are registers name in assembly cryptic

Why are registers named so short - EAX, EBX,...etc They could have easily made the names more descriptive rather than encrypted like that.
Amit wadhwa's user avatar
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Can a single core processor be MIMD?

I was wondering for if a single core processor can be MIMD? or MISD? or SIMD? I thought MIMD's requirement is multicore, but I am not sure about this
user132604's user avatar
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How do windows executables run on both AMD CPUs and Intel CPUs?

Do they contain instructions for both CPUs or do the CPUs have the same instruction set? Assuming they weren't compiled to an intermediate language (although even then, I think the intermediate ...
Hormoz's user avatar
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CPU overused vs RAM normal usage, RAM overused vs CPU normal usage

I got asked this question in an interview, where they showed me graphs of CPU being overused and RAM being normally used, and graphs of vice versa. What deductions can we make from this, and how can ...
James Flanagin's user avatar
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Building an ALU on nandgame's website

I'm working on nandgame's website found here. I'm working on the ALU and here is an image of my implementation: My Implementation: And I compared it to this website's solution: Solution However when ...
Francis Cugler's user avatar
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Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the architecture most likely to have?

Working through some material on CPU architecture and am unsure on the following question: Suppose that an instruction encoding format has 4 bits for argument registers. How many registers is the ...
Gooze_Berry's user avatar
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How many clock cycles

Actually it differs from CPU to CPU but it is possible to choose a mainstream CPU technology used in moderate servers or home computers. How many clock cycles it takes to read a file of 50KB from ...
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