Questions tagged [instruction-set]
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Is a CPU with a hybrid Instruction Set Architecture (ISA) possible?
Is it possible to (theoretically) develop a CPU having a hybrid ISA such that half of the cores in it use the x86 architecture and the other half uses the ARM architecture? The x86 cores would run the ...
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Learn computer architecture and organisation via an oversimplified machine
I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
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Can a CPU instruction be split into 2 inputs?
Let's say there was a CPU with an input bus of 4 bits and the 4 bits are the opcode then the next 4 bits are the operand. It would just be an 8-bit instruction split in two. Is this possible and how ...
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How does a CPU jump to a instruction thats no longer in ram?
Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
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how to get the high 32-bit of the answer of two 32-bit integer multiple?
Recently, I study the instruction set of riscv32 and face a order as "mulh" which tends to multiply two 32-bits signed integers and store the high 32 value into the register.
And here comes ...
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Is a specialized hardware instruction always faster than a software implementation, and if so, is there a general reason?
I started wondering this after reading about the x86-SSE instruction rsqrtss being faster (and more accurate) than the Fast inverse square root. I have also read ...
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What is a procedure?
Non-computer scientist here, trying to understand what SICP (Structure and Interpretation of Computer Programs) means by a procedure, whether it matches the dictionary definition, and also how a ...
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How are processor instructions stored in RAM?
I've recently been designing a simple 8-bit microprocessor, similar to the Intel 8008. It doesn't make use of anything advanced as pipelining, as my knowledge isn't at that level yet to know how to ...
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How does instruction set architecture affects clock rate?
According to the computer organization and design RISC-V 2nd edition 2020, section 1.5, the following table states that ISA affects clock rate.
Hardware or software component
Affects what?
How?
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Why scopes in general do not have prologue and epilogue instructions?
Data only accessible in a scope, seems to still be maintained by the stack. What is the reason that entering and exiting scopes (in general) does not do the same "prologue and epilogue" ...
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How can an instruction be fetched every cycle?
From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
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What kind of binary compatibility is present for 2 processors sharing an Instruction Set?
Consider Intel x86 and AMD x86 Processors. As I understand, since they use the same Instruction Set, in theory an application compiled for Intel x86 processor would run without any modification on ...
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