Questions tagged [memory-access]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
1
vote
1answer
31 views

Segmented address / normal virtual address

In a cpu with segmented memory, can an address only be accessed with a segmented address, or can a normal virtual address also be used?
2
votes
2answers
31 views

Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
2
votes
0answers
15 views

What are address shadows?

In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
0
votes
1answer
29 views

Connection of different buses to memory

The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
0
votes
0answers
13 views

Computer Architecture, Memory Interleaving. Decoding step can be interleaved?

A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ ...
0
votes
0answers
17 views

What is the Memory Bandwidth Usage in a Program Related to?

We can use performance counter tools to check the memory bandwidth usage while a program is running. I want to ask what is this memory bandwidth related to? What parameters are involved in memory ...
0
votes
0answers
20 views

Comparing Registers with 16-bits

I am given with this information: "CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=...
0
votes
0answers
24 views

Reading process memory of computer A on computer B?

So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
0
votes
0answers
18 views

How memory address decoders works?

I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube 4 is the input (address bus) and 16 is the output. 4 X 16 can only access 16 unique addresses. What if I have thousands of ...
0
votes
0answers
18 views

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh ...
0
votes
2answers
43 views

Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
0
votes
0answers
26 views

Unbanked access, banked access and common memory access

What are they and what are their differences? Unbanked access Banked access Common memory access [EDIT] This question is originated from my reading of MPLAB XC8 PIC Assembler User's Guide where the ...
2
votes
0answers
29 views

How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
1
vote
1answer
86 views

How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
0
votes
0answers
23 views

What bus DIMM (RAM module) uses?

I know there are different types of BUS like PCI, SCSI, ISA etc. What specific type of bus (for address bus and data bus) do a DIMM module use ?
0
votes
0answers
12 views

Cache Blocks Direct Mapping

If the main memory address has 18 bits (7 for tag,7 for line and 4 for word) and each word is 8 bits. I found that the main memory capacity is 256-KBytes, total cache lines is 128 line, total cache ...
2
votes
1answer
98 views

Efficiently storing and modifying a reorderable data structure in a database

I'm trying to create a list curation web app. One thing that's important to me is being able to drag-and-drop reorder items in the list easily. At first I thought I could just store the order of each ...
0
votes
3answers
49 views

CPU Registers and Computation

How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit? For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
0
votes
2answers
61 views

Big-endian systems and the smallest memory address

I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
0
votes
1answer
345 views

Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
1
vote
1answer
138 views

Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
0
votes
0answers
28 views

Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
0
votes
2answers
54 views

Understanding memory leaks in C/C++ [closed]

I was looking at an example here: https://blog.parasoft.com/finding-memory-leaks-in-c ...
0
votes
0answers
27 views

If there is a cache miss can we consider extra memory accesses because it has to fetch data from the main memory?

A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store ...
1
vote
3answers
283 views

The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
3
votes
2answers
79 views

Why are primitive types stored in a stack in systems level software?

Firstly 2 disclaimers, I am very new to the concept of a stack at a low level. I've only encountered it because I'm learning rust and the docs mention it. Secondly, I am aware of another similar ...
1
vote
0answers
23 views

Minimising total access time to elements in an array which is accessed sequentially

Starting with two examples: for(i = 1; i<10; i++) {B[i] = 0;} for(i = 1; i<10; i++) {B[2i] = 0;} In the first example, ...
1
vote
3answers
93 views

Does RAM get an indication of data size required

Pre-information: I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer Question: Does RAM get some kind of indication as to ...
2
votes
2answers
46 views

Can the same machine word sometimes be data and sometimes be code?

I have a question about machine words. We have data and a code segment in the memory which is addressed. If we take a word from it and let's say it is a code (instruction), and another one is some ...
5
votes
1answer
522 views

How does a TLB lookup compare all keys simultaneously?

I am reading OS Concepts dinosaur book which says, "Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared ...
3
votes
1answer
43 views

Is PREFETCH an asynchronous operation?

I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
2
votes
1answer
74 views

How memory controller reads from RAM with O(1) time complexity?

I am trying to understand how a RAM memory controller gets data with instant access while reading through the memory. Let's say initially, ram gets the data at address 0 and then to get the data at ...
1
vote
0answers
16 views

Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
0
votes
1answer
1k views

What's the maximum memory address space that the processor can access directly if it connected to a 16-bit memory?

The question is the following: 3. Given a hypothetical microprocessor which generates a 16-bit address (assume that the program counter and address registers are 16 bits wide) and has a 16 bit data ...
0
votes
1answer
91 views

Distinction between paging and segmentation?

In my operating systems textbook, there is a paragraph which states: As for the contents of each PTE, we have a number of different bits in there worth understanding at some level. A valid bit is ...
3
votes
1answer
54 views

Are all data structures in the von Neumann architecture based on the array, or array-like?

I am an old Pythonista now learning C and how various data structures and types are implemented, such as binary trees and hash tables. Learning about the latter, leads me understand that the hash ...
0
votes
2answers
3k views

Difference between Sequential ,Direct and Random acess with their acess time

I'm stuck on a point while reading about these different accessing methods. As per author. Sequential access Memory is organized into units of data, called records.Access must be made in a ...
2
votes
1answer
2k views

Byte addressable vs Word addressable

I am trying to understand the difference between byte addressing and word addressing. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The ...
0
votes
2answers
100 views

Understanding memory mapping conceptually

I've already read several blogs and questions on stack exchange, but I'm unable to grasp what the real drawbacks of memory mapped files are. I see the following are frequently listed: You can't ...
1
vote
1answer
54 views

In a DBMS what are the implementation details that make set operations faster than cursors?

What are the low level implementation details that make set based operations exponentially faster than iterative processes, like cursors? At a memory level how does a set operation "touch" the data ...
1
vote
1answer
76 views

Clarification on interplay between cache line size and read/write sizes

Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes. According to my understanding, we use a number ...
0
votes
2answers
74 views

How does the memory of a 64bit and 32bit processor work

In this article, the author states that a 64bit processor can theoretically reference 2^64 bytes of memory. What does he mean by this statement, or rather the word, reference? Also, I visualize the ...
0
votes
0answers
17 views

Memory interfacing problem [duplicate]

I've learnt that the memory interfacing problem is used when we need to connect a memory that has lesser number of locations to a processor that has more address lines. For eg. Connecting memory chips ...
1
vote
1answer
243 views

Address and data bus

When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about? Also, why is the address bus unidirectional, as opposed to the data bus? ...
2
votes
1answer
595 views

Why don't integer multiplication algorithms use lookup tables?

It seems to me that we can use lookup tables for multiplication of two integers of size $\log(n)/2$, and that the number of entries for each table of these numbers should be $O(n)$. Now, multiplying ...
1
vote
0answers
22 views

Addresses with no memory allocated

I've read that a program can crash if it tries to access addresses with no memory allocated. But, how is it possible that an address has no memory allocated? When does it happen?
0
votes
1answer
147 views

Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
0
votes
0answers
78 views

Storing binary tree with arbitrarily sized nodes without linked-list or large 32-bit pointers

So you can store a binary tree without pointers using a 1-D array: Binary Trees can be represented using 1-D array in memory(Fig 1).The rule to store binary tree in array are : The values of ...
0
votes
1answer
370 views

Memory Mapping Segment

I read that "Memory Mapping Segment"/"memory mapped file" is a segment of the virtual memory of a process, where a file or file-like Ressource is loaded into. It is for high performance file I/O. I ...
0
votes
1answer
54 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...