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Questions tagged [memory-access]

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1answer
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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0answers
26 views

Storing binary tree with arbitrarily sized nodes without linked-list or large 32-bit pointers

So you can store a binary tree without pointers using a 1-D array: Binary Trees can be represented using 1-D array in memory(Fig 1).The rule to store binary tree in array are : The values of ...
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1answer
8 views

Memory Mapping Segment

I read that "Memory Mapping Segment"/"memory mapped file" is a segment of the virtual memory of a process, where a file or file-like Ressource is loaded into. It is for high performance file I/O. I ...
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1answer
26 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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0answers
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Associative cache finding the tag and word number

An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes. I'm unsure how to find ...
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0answers
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Disk Scheduling for a Fragmented Hard-Drive

Recently In class I have been learning about simple disk scheduling algorithms such as FCFS, STTF, LOOK, LOOK-SCAN etc. From my understanding these algorithms schedule I/O requests depending on which ...
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0answers
31 views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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1answer
24 views

Registers in a CPU

https://en.wikipedia.org/wiki/Processor_register So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
0
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1answer
210 views

Architecture - calculating miss penalty

I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) ...
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1answer
711 views

Cache effective access time calculation

In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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2answers
39 views

what is the meaning of hit time?

Average memory access time = Hit time + Miss rate * miss penalty Assume a computer with only one cache level. What is the exact meaning of hit time? Is it the ...
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0answers
45 views

Why is the method of im2col with GEMM is more efficient than the method of direction implementation with SIMD in CNN

The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement convolutional layers is to expand the image into a ...
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3answers
60 views

Loading a word from byte-addressable cache

I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead.. So, my question is pretty much the same as the one in the question I ...
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1answer
73 views

accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
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0answers
26 views

What are data address generators?

I have come across the term Data Address Generator (DAG), which is used in Digital Signal Processors (DSPs) for memory access. What I do not understand is why can't memory be accessed directly with ...
1
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1answer
63 views

AMAT calculation

I was just solving an exercise when the answer of this suprised me : We have a memory hierarchy built with 2 levels of caches and a main memory, the access time of the L1 is 1 cycle, for L2 it's 10 ...
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1answer
61 views

Valid bit incoherence between TLB and Page Table

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
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1answer
28 views

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
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2answers
47 views

How does RAMDAC get notified about framebuffer write?

I'm learning computer graphics, and I read this course lecture in order to understand how graphics I/O works under the hood. But the following explanation was not very clear to me: The values in ...
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1answer
31 views

Linked List fundamental concepts [closed]

I am trying to understand the basics of Linked List. The definition of my LinkedList class is as follows: ...
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1answer
47 views

Question on “Hitting the memory wall, implications of the obvious”

I'm reading through a short paper about hitting the memory wall and I'm struggling to understand how exactly said wall will be hit. The equation for average access time is fairly simple ...
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2answers
131 views

How can a 16-bit or more processor store a byte in a byte-addressed memory

I am confused as to how a 16-bit (or 32, 64) processor can store multiple adjacent bytes at once without supplying multiple addresses For example say we have (16-bit processor) 0xABCD starting at ...
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0answers
23 views

Understanding the notation and concept behind March Tests

Some background on my question: I have done some research into March Tests that are essentially access patterns for DRAM. One example of these march tests in the MATS+ algorithm shown below with (I ...
0
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1answer
51 views

How should I “read” a dereference operator?

For example, when I look at some code like int x = 1; int * y = &x; I can read it like ...
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0answers
21 views

Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
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1answer
29 views

Does having more bus in the computer increasing speed? [closed]

Whát i mention here is for having 2x bus will increasing 2x memory access speed like 3x will have 3x memory access speed like that !
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1answer
279 views

Cache efficient matrix multiplication

Consider these matrices: $A=\begin{bmatrix}1 & 2\\3 & 4\end{bmatrix}$ $B=\begin{bmatrix}-1 & -2\\-3 & -4\end{bmatrix}$ Using standard algorithm: $C=\begin{bmatrix}1*-1+2*-3 & 1*...
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1answer
793 views

Why sequential access is faster than random access?

I am currently getting really confused of two documents I read: one is from Wikipedia that states: The opposite is sequential access, where a remote element takes longer time to access. and this ...
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1answer
3k views

If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?

Let's say we are working with a system that has 40 physical address bits. The total physical address space (assuming byte-addressable memory) is $2^{40}$ bytes, or 1 TiB. And if virtual addresses are ...
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2answers
263 views

How do Hard Drives Send and Recieve Data?

Ok. I know this is probably a commonly asked question. Before you refer me to a site or answer this yourself, I ask for you to please read this through. I have been into computers and electronics for ...
0
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1answer
85 views

Exactly why the time taken by 'memory reads', is not considered while calculating time complexity of an algorithm?

I am sorry if I sound repetitive(I've asked a similar sounding question earlier - Relevance of memory reads while calculating the time complexity of an algorithm). Actually, it didn't answered my ...
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0answers
66 views

What happens when accessing 0x00ABBA?

Given the following page table with a 24 Bit virtual address and 4KB page size and 4 byte long entries (%X means hexadecimal values): I don't understand how to translate e.g. address %X00ABBA here. I ...
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5answers
471 views

Relevance of memory reads while calculating the time complexity of an algorithm

Can there be a genuine algorithm in which number of memory reads far outnumber the no. of operations performed? For example, number of memory reads scale with n^2, while no. of operations scale with ...
0
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1answer
333 views

How is segmentation different from multiprogramming with fixed partition?

As seen here: It works same like multiprogramming with fixed partition and also the memory is contiguous as well. How is it different and especially non-contiguous? What's happening here?
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2answers
557 views

Since physical memory is the RAM where is logical memory stored on the computer?

Since logical memory maps to the RAM (physical memory) it has be stored somewhere right and it will obviously take large bunch of memory of itself. Where is it stored?
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1answer
66 views

Calculating fractions of accesses from various levels of memory? (L2 - Main)

I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer. The question goes; ...
2
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2answers
2k views

Row Major Vs Column Major

People prefer accessing a 2D array in row-major order than column-major order. Why row-major is efficient? Is there some advantage of row major as compare to column major wrt memory.
1
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1answer
41 views

New Idea for accessing memory across an inter-network connected system

I have the following idea for a network-based operating system. Suppose we have two computers A and B in a network. If computer B wants to access the memory of computer A, it can access by using the ...
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2answers
625 views

Insertion sort vs Merge sort - memory access

I am a computer science sophomore doing a data structures and algorithms course. My professor said that insertion sort requires random access, while merge sort does not. According to him, the ...
3
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1answer
20 views

how does an object find the reference to its instance variables

I'm trying to understand how instance variables for a given object are stored for easy access later on. For some background, I understand that if you have a reference to an array it is very easy for ...
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2answers
793 views

Are constants faster than variables?

It's said that constant references within a program are replaced by the value at compile time, where as, variable references will need to be looked up at run time - making them slower. Yeah, it ...
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0answers
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Does weak consistency allow reordering of events?

I am on studying a consistency model: weak consistency. weak consistency This model was first defined by Dubois et al. (1986), by saying that it has three properties: Accesses to synchronization ...
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2answers
665 views

RAM can be accessed hundreds of times faster than a hard drive. Explain How?

I have been reading this for quiet a long time that "RAM can be accessed hundreds of times faster than a hard drive". But, no one has been able to explain it properly. I searched on Internet and ...
1
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1answer
184 views

byte addressing memory and 32 bit bus

Say I have total 4 bytes on 1 byte addressable memory, with a 32 bit bus. If I move value at 0'th address to one of the registers will system grab all 32 bits (all 4 bytes) through bus from memory, ...
0
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1answer
352 views

Direct-mapping cache

I had this question on a previous homework assignment and was unable to answer it. I've done some research and am not really able to find anything that clears this up for me. Would appreciate any help ...
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0answers
132 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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0answers
148 views

What is the algorithmic complexity of DFS under the cache oblivious model?

Consider the basic non-recursive DFS algorithm on a graph G=(V,E) (python-like pseudocode below) that uses array-based adjacency lists, a couple of arrays of size V, and a dynamic array stack of size &...
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5answers
8k views

How do computers remember where they store things?

When a computer stores a variable, when a program needs to get the variable's value, how does the computer know where to look in memory for that variable's value?
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2answers
3k views

How does RAM is shared in multi core environment?

I learnt that multi core processors have more than one processing units( i.e. the main executing units ALU etc.) and they are better at performance. I want to know how they share Physical memory. I'll ...
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0answers
218 views

Fully associative cache - calculate address tag bits?

I have the following task: Main memory capacity = 64MB (B = byte) Cache capacity = 64KB Block size = 16B Processor addressed information with address A = 0052A622h Calculate address tag ...