Questions tagged [memory-access]

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Are the number of entries in the TLB(Translation Lookaside Buffer) limited?

If not, then why aren't all the pages loaded into the TLB so that TLB misses never happen.
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How does changing cache size and/or block size affect the hit rate of the for loops in the following code?

I am working on practice problems to study for an upcoming exam. I am given the following piece of code: ...
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What is the maximum memory address space that microprocessor can access directly if a 16-bit memory module is interfaced with a 32-bit microprocessor?

The Complete question is as follows : Consider a single-address 32-bit microprocessor with 32-bit address bus and 32-bit data bus. Its instructions composed of 1-byte opcode and 3-byte operand address....
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Virtual Memory - Calculating Page Table Size and Other Attributes

Im struggling to understand the answer to a question: Consider a system with 2MiB physical memory and 4GiB virtual memory. Page size is 4KiB. If we choose to store seven information bits in each PTE, ...
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The memory a page table occupies and finding the # of pages within it

Was doing some practice and saw this question: Assume we’re working on a machine which has the following parameters: • 16GiB of physical memory • 22 bit virtual addresses • 128B pages • Each PTE in ...
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Find offset and page number given paged virtual memory address

I ran into this question in class: Assume a machine that is 64-bit and has 8GB memory. They use a paged virtual memory where the page size is 4KB. You run the following program: ...
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Select signals for memory mapped into common address space

I just got a hobby of studying this topic and it is quite intriguing. In one of the books, I came up with the following question: A computing hardware is to be designed with a processor generating ...
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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Finding upper bound on number of I/Os needed to generate all permutations of some input in external memory

The general approach outlined in this paper in its proof of the lower bound on the average number of I/Os needed to obtain a given permutation of some input in external memory is as follows. Note that ...
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Page fault rate while calculating effective access time

So here is a question regarding calculating effective access time (EAT). So the question is : suppose a system with an average page page-fault service time of 6 milliseconds and a memory access time ...
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Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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Segmented address / normal virtual address

In a cpu with segmented memory, can an address only be accessed with a segmented address, or can a normal virtual address also be used?
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Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
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What are address shadows?

In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
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Connection of different buses to memory

The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
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Computer Architecture, Memory Interleaving. Decoding step can be interleaved?

A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ ...
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What is the Memory Bandwidth Usage in a Program Related to?

We can use performance counter tools to check the memory bandwidth usage while a program is running. I want to ask what is this memory bandwidth related to? What parameters are involved in memory ...
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Comparing Registers with 16-bits

I am given with this information: "CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=...
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Reading process memory of computer A on computer B?

So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
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How memory address decoders works?

I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube 4 is the input (address bus) and 16 is the output. 4 X 16 can only access 16 unique addresses. What if I have thousands of ...
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A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips

A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh ...
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Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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Unbanked access, banked access and common memory access

What are they and what are their differences? Unbanked access Banked access Common memory access [EDIT] This question is originated from my reading of MPLAB XC8 PIC Assembler User's Guide where the ...
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
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How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
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What bus DIMM (RAM module) uses?

I know there are different types of BUS like PCI, SCSI, ISA etc. What specific type of bus (for address bus and data bus) do a DIMM module use ?
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Cache Blocks Direct Mapping

If the main memory address has 18 bits (7 for tag,7 for line and 4 for word) and each word is 8 bits. I found that the main memory capacity is 256-KBytes, total cache lines is 128 line, total cache ...
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Efficiently storing and modifying a reorderable data structure in a database

I'm trying to create a list curation web app. One thing that's important to me is being able to drag-and-drop reorder items in the list easily. At first I thought I could just store the order of each ...
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CPU Registers and Computation

How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit? For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
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Big-endian systems and the smallest memory address

I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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965 views

Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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314 views

Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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Understanding memory leaks in C/C++ [closed]

I was looking at an example here: https://blog.parasoft.com/finding-memory-leaks-in-c ...
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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
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Why are primitive types stored in a stack in systems level software?

Firstly 2 disclaimers, I am very new to the concept of a stack at a low level. I've only encountered it because I'm learning rust and the docs mention it. Secondly, I am aware of another similar ...
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Minimising total access time to elements in an array which is accessed sequentially

Starting with two examples: for(i = 1; i<10; i++) {B[i] = 0;} for(i = 1; i<10; i++) {B[2i] = 0;} In the first example, ...
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Does RAM get an indication of data size required

Pre-information: I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer Question: Does RAM get some kind of indication as to ...
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Can the same machine word sometimes be data and sometimes be code?

I have a question about machine words. We have data and a code segment in the memory which is addressed. If we take a word from it and let's say it is a code (instruction), and another one is some ...
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How does a TLB lookup compare all keys simultaneously?

I am reading OS Concepts dinosaur book which says, "Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared ...
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Is PREFETCH an asynchronous operation?

I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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How memory controller reads from RAM with O(1) time complexity?

I am trying to understand how a RAM memory controller gets data with instant access while reading through the memory. Let's say initially, ram gets the data at address 0 and then to get the data at ...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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What's the maximum memory address space that the processor can access directly if it connected to a 16-bit memory?

The question is the following: 3. Given a hypothetical microprocessor which generates a 16-bit address (assume that the program counter and address registers are 16 bits wide) and has a 16 bit data ...
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Distinction between paging and segmentation?

In my operating systems textbook, there is a paragraph which states: As for the contents of each PTE, we have a number of different bits in there worth understanding at some level. A valid bit is ...
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Are all data structures in the von Neumann architecture based on the array, or array-like?

I am an old Pythonista now learning C and how various data structures and types are implemented, such as binary trees and hash tables. Learning about the latter, leads me understand that the hash ...
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Difference between Sequential ,Direct and Random acess with their acess time

I'm stuck on a point while reading about these different accessing methods. As per author. Sequential access Memory is organized into units of data, called records.Access must be made in a ...
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Byte addressable vs Word addressable

I am trying to understand the difference between byte addressing and word addressing. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The ...
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Understanding memory mapping conceptually

I've already read several blogs and questions on stack exchange, but I'm unable to grasp what the real drawbacks of memory mapped files are. I see the following are frequently listed: You can't ...