Questions tagged [memory-access]
The memory-access tag has no usage guidance.
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Is this how endianess work relative to memory?
So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things.
Here is how I look at ...
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How can computers tell where the beginning and end of file/packet/frame headers are?
I'd like to know how a computer can determine the beginning and end of certain file components (attributes, headers, frame/packet/segment headers etc.) when these components can be omitted or added in ...
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How are processor instructions stored in RAM?
I've recently been designing a simple 8-bit microprocessor, similar to the Intel 8008. It doesn't make use of anything advanced as pipelining, as my knowledge isn't at that level yet to know how to ...
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How hardware write a byte in memory?
I want to know how hardwares write a byte in memory?
If there is difference between writing process in RAM and ROM I would like to know as well.
Specially I want to know:
Is hardware writes values ...
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compute cache miss rate by given code
I have been trying to solve questions like this before but I have stumbled in difficulty to track the the space of the cache.
so there is an example of a question like this:
Given the code:
...
user152808
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Are there absolute reasons to prefer row/column-major memory ordering?
I've heard it said that "fortran uses column-major ordering because it's faster" but I'm not sure that's true. Certainly, matching column-major data to a column-major implementation will ...
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Are all CPU computations done using registers?
From my understanding, a CPU register is a temporary storage or working location built into the CPU itself. The CPU includes some functional units such as the ALU (which is part of the chip, as far as ...
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Performance of CPU with two caches
I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this
Cache L1 ...
user145450
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Assembly language addressing mode instructions
I am studying assembly language. I feel very difficult in understanding few instruction.
ADD R1,R2,[R3]
ADD R1, R2, R3
What is the difference between these two instructions. I think second instruction ...
user145450
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Definition of the term "access efficiency" in the context of computer systems
In a two-level virtual memory, the memory access time for main memory, $t_M=10^{−8}$ sec, and the memory access time for the secondary memory, $t_D=10^{−3}$ sec. What must be the hit ratio, $H$ such ...
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Can a software program be stored in just one memory cell?
I would define a software program as at least one line of code stored in at least one computer system's memory cell.
Can a software program be stored in just one memory cell or rather (due to binary ...
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How the data is transferred from main memory to hard disk?
I understand that data is transferred from the main memory to the CPU and vise versa using the data bus. But, I am unable to understand, how the data is being transferred from the main memory to the ...
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Are sample memory access traces/dumps available, and where?
I am looking for a realistic physical memory access trace/dump of significant, but not insane, length (on the order of 1M accesses) for the purpose of cache simulation. Preferably for a 16-bit or 32-...
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What are pointers in low-level language like C
I was trying to understand pointers by watching YouTube videos. However, I could not understand
How do they work?
Why do we use them?
When do we use them?
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity
Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
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Words in computer's memory
I don't know much about memory. Here are some lines from CLRS:
The words in a computer memory are typically addressed by integers from 0
to $M - 1$, where $M$ is a suitably large integer. In many ...
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What is the nature of the two bits of data held in a computer memory cell?
I hope this question doesn't offend anyone. I start off by saying that I have and always had difficulty understand the language used in computer science so I have to interpret everything into the ...
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Are the number of entries in the TLB(Translation Lookaside Buffer) limited?
If not, then why aren't all the pages loaded into the TLB so that TLB misses never happen.
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Find offset and page number given paged virtual memory address
I ran into this question in class:
Assume a machine that is 64-bit and has 8GB memory. They use a paged virtual memory where the page size is 4KB. You run the following program:
...
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Select signals for memory mapped into common address space
I just got a hobby of studying this topic and it is quite intriguing. In one of the books, I came up with the following question:
A computing hardware is to be designed with a processor generating ...
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?
A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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Formula to see where a memory address can be depicted in cache?
I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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Query Regarding Direct cache mapping [closed]
Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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Segmented address / normal virtual address
In a cpu with segmented memory, can an address only be accessed with a segmented address, or can a normal virtual address also be used?
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Calculate the effective access time
This question seems to be causing a lot of debate and I'm wondering whether my working is correct.
A computer with a single cache (access time 20ns) and main memory (access
time 500ns) also uses the ...
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What are address shadows?
In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
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Connection of different buses to memory
The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
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Comparing Registers with 16-bits
I am given with this information:
"CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal,
flag values will be ZF=1, CF=0,
if the first
operands value is greater flag values will be ZF=...
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Reading process memory of computer A on computer B?
So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
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How memory address decoders works?
I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube
4 is the input (address bus) and 16 is the output.
4 X 16 can only access 16 unique addresses.
What if I have thousands of ...
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Storage in registers
Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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Unbanked access, banked access and common memory access
What are they and what are their differences?
Unbanked access
Banked access
Common memory access
[EDIT]
This question is originated from my reading of MPLAB XC8 PIC Assembler User's Guide where the ...
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How is readiness of instructions fetched from RAM signaled to the CPU?
In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
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How does the cache / memory know where to return results of read requests to?
The pipeline of a modern processor has many stages that may issue read
requests to main memory, e.g. in fetching the next command or loading
some memory location into a register. How is the result of ...
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Efficiently storing and modifying a reorderable data structure in a database
I'm trying to create a list curation web app. One thing that's important to me is being able to drag-and-drop reorder items in the list easily. At first I thought I could just store the order of each ...
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CPU Registers and Computation
How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit?
For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
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Big-endian systems and the smallest memory address
I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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Average access time in two level cache system
In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Hard Drive Seek Time using FIFO, SSF, SCAN
A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
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Size of the data bus connecting CPU cache and RAM?
I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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Understanding memory leaks in C/C++ [closed]
I was looking at an example here:
https://blog.parasoft.com/finding-memory-leaks-in-c
...
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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?
Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e
The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ?
a)...
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Why are primitive types stored in a stack in systems level software?
Firstly 2 disclaimers, I am very new to the concept of a stack at a low level. I've only encountered it because I'm learning rust and the docs mention it. Secondly, I am aware of another similar ...
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Minimising total access time to elements in an array which is accessed sequentially
Starting with two examples:
for(i = 1; i<10; i++) {B[i] = 0;}
for(i = 1; i<10; i++) {B[2i] = 0;}
In the first example, ...
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Does RAM get an indication of data size required
Pre-information:
I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer
Question:
Does RAM get some kind of indication as to ...
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Can the same machine word sometimes be data and sometimes be code?
I have a question about machine words. We have data and a code segment in the memory which is addressed. If we take a word from it and let's say it is a code (instruction), and another one is some ...
user115005
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How does a TLB lookup compare all keys simultaneously?
I am reading OS Concepts dinosaur book which says, "Each entry in the TLB consists of two parts: a key (or tag) and a value. When the associative memory is presented with an item, the item is compared ...
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Is PREFETCH an asynchronous operation?
I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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How memory controller reads from RAM with O(1) time complexity?
I am trying to understand how a RAM memory controller gets data with instant access while reading through the memory. Let's say initially, ram gets the data at address 0 and then to get the data at ...
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Approximate cache size & cache line size from optimal tile size
I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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