Questions tagged [memory-access]

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Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
2 votes
1 answer
2k views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
1 vote
3 answers
1k views

Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
2 votes
4 answers
7k views

Difference between Sequential ,Direct and Random acess with their acess time

I'm stuck on a point while reading about these different accessing methods. As per author. Sequential access Memory is organized into units of data, called records.Access must be made in a ...
1 vote
2 answers
435 views

Find offset and page number given paged virtual memory address

I ran into this question in class: Assume a machine that is 64-bit and has 8GB memory. They use a paged virtual memory where the page size is 4KB. You run the following program: ...
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2 answers
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Select signals for memory mapped into common address space

I just got a hobby of studying this topic and it is quite intriguing. In one of the books, I came up with the following question: A computing hardware is to be designed with a processor generating ...
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1 answer
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How many bits do the pointers take?

So I am covering succinct trees, and in the lecture, it mentioned that "An n-node tree takes 2n pointers or 2n lg n bits (can be easily reduced to n lg n + O(n) bits). First, question is why ...
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1 answer
32 views

Same Address and Write signal for two block of RAM?

I don't know if I asked the question in correct way but I will try to explain what's the thing I am not getting. I am currently reading book titled "Code: The Hidden Language of Computer Hardware ...
2 votes
1 answer
144 views

Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
16 votes
3 answers
10k views

If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?

Let's say we are working with a system that has 40 physical address bits. The total physical address space (assuming byte-addressable memory) is $2^{40}$ bytes, or 1 TiB. And if virtual addresses are ...
1 vote
2 answers
112 views

Comparing Registers with 16-bits

I am given with this information: "CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=...
1 vote
3 answers
101 views

Is this how endianess work relative to memory?

So I've been trying to understand endianess for the past couple of days but I'm not sure if I'm overthinking this or not and I don't have anyone I can ask to confirm things. Here is how I look at ...
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2 answers
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How does a CPU jump to a instruction thats no longer in ram?

Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
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DMA mode: burst or cycle stealing -- how to know and set? What is blocked?

What component and mechanism determines which DMA transfer mode is used? How can be identified what DMA mode is used by a device, let's say on Linux? Let's consider a contemporary AMD or Intel x86-64 ...
2 votes
3 answers
2k views

Why don't integer multiplication algorithms use lookup tables?

It seems to me that we can use lookup tables for multiplication of two integers of size $\log(n)/2$, and that the number of entries for each table of these numbers should be $O(n)$. Now, multiplying ...
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1 answer
749 views

Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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1 answer
102 views

How can computers tell where the beginning and end of file/packet/frame headers are?

I'd like to know how a computer can determine the beginning and end of certain file components (attributes, headers, frame/packet/segment headers etc.) when these components can be omitted or added in ...
1 vote
1 answer
854 views

How are processor instructions stored in RAM?

I've recently been designing a simple 8-bit microprocessor, similar to the Intel 8008. It doesn't make use of anything advanced as pipelining, as my knowledge isn't at that level yet to know how to ...
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0 answers
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How hardware write a byte in memory?

I want to know how hardwares write a byte in memory? If there is difference between writing process in RAM and ROM I would like to know as well. Specially I want to know: Is hardware writes values ...
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1 answer
539 views

compute cache miss rate by given code

I have been trying to solve questions like this before but I have stumbled in difficulty to track the the space of the cache. so there is an example of a question like this: Given the code: ...
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2 answers
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Assembly language addressing mode instructions

I am studying assembly language. I feel very difficult in understanding few instruction. ADD R1,R2,[R3] ADD R1, R2, R3 What is the difference between these two instructions. I think second instruction ...
6 votes
3 answers
1k views

Are there absolute reasons to prefer row/column-major memory ordering?

I've heard it said that "fortran uses column-major ordering because it's faster" but I'm not sure that's true. Certainly, matching column-major data to a column-major implementation will ...
0 votes
2 answers
187 views

Are all CPU computations done using registers?

From my understanding, a CPU register is a temporary storage or working location built into the CPU itself. The CPU includes some functional units such as the ALU (which is part of the chip, as far as ...
2 votes
1 answer
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What is M referring to when talking about memory size( 4M x 8)

In the following paragraph its talking about memory and it throws M into the L X W of memory notation and i'm confused on how 4M = 2^22. Thanks in advance PARAGRAPH: Memory is built from random ...
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Performance of CPU with two caches

I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this Cache L1 ...
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0 answers
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Definition of the term "access efficiency" in the context of computer systems

In a two-level virtual memory, the memory access time for main memory, $t_M=10^{−8}$ sec, and the memory access time for the secondary memory, $t_D=10^{−3}$ sec. What must be the hit ratio, $H$ such ...
1 vote
4 answers
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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
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2 answers
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Can a software program be stored in just one memory cell?

I would define a software program as at least one line of code stored in at least one computer system's memory cell. Can a software program be stored in just one memory cell or rather (due to binary ...
1 vote
1 answer
108 views

Reading process memory of computer A on computer B?

So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
1 vote
0 answers
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How the data is transferred from main memory to hard disk?

I understand that data is transferred from the main memory to the CPU and vise versa using the data bus. But, I am unable to understand, how the data is being transferred from the main memory to the ...
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1 answer
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Are sample memory access traces/dumps available, and where?

I am looking for a realistic physical memory access trace/dump of significant, but not insane, length (on the order of 1M accesses) for the purpose of cache simulation. Preferably for a 16-bit or 32-...
3 votes
2 answers
804 views

What are pointers in low-level language like C

I was trying to understand pointers by watching YouTube videos. However, I could not understand How do they work? Why do we use them? When do we use them?
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2 answers
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Are the number of entries in the TLB(Translation Lookaside Buffer) limited?

If not, then why aren't all the pages loaded into the TLB so that TLB misses never happen.
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1 answer
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity

Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
2 votes
1 answer
128 views

Words in computer's memory

I don't know much about memory. Here are some lines from CLRS: The words in a computer memory are typically addressed by integers from 0 to $M - 1$, where $M$ is a suitably large integer. In many ...
3 votes
1 answer
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What is the nature of the two bits of data held in a computer memory cell?

I hope this question doesn't offend anyone. I start off by saying that I have and always had difficulty understand the language used in computer science so I have to interpret everything into the ...
2 votes
1 answer
385 views

What are address shadows?

In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
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2 answers
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Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
4 votes
3 answers
16k views

Row Major Vs Column Major Order: 2D arrays access in programming languages

Programmers prefer accessing a 2D array in Row-Major Order rather than Column-Major Order, Why? Are there some advantages/benefits of accessing a 2D array in row-major as compare to column-major? ...
2 votes
1 answer
275 views

Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
1 vote
1 answer
2k views

Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
2 votes
2 answers
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In a DBMS what are the implementation details that make set operations faster than cursors?

What are the low level implementation details that make set based operations exponentially faster than iterative processes, like cursors? At a memory level how does a set operation "touch" the data ...
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3 answers
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Loading a word from byte-addressable cache

I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead.. So, my question is pretty much the same as the one in the question I ...
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1 answer
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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1 answer
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Segmented address / normal virtual address

In a cpu with segmented memory, can an address only be accessed with a segmented address, or can a normal virtual address also be used?
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1 answer
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Connection of different buses to memory

The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
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How memory address decoders works?

I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube 4 is the input (address bus) and 16 is the output. 4 X 16 can only access 16 unique addresses. What if I have thousands of ...
9 votes
2 answers
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Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
4 votes
2 answers
20k views

Cache effective access time calculation

In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
2 votes
1 answer
278 views

Does weak consistency allow reordering of events?

I am on studying a consistency model: weak consistency. weak consistency This model was first defined by Dubois et al. (1986), by saying that it has three properties: Accesses to synchronization ...