Questions tagged [memory-access]

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Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
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Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
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Find offset and page number given paged virtual memory address

I ran into this question in class: Assume a machine that is 64-bit and has 8GB memory. They use a paged virtual memory where the page size is 4KB. You run the following program: ...
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Select signals for memory mapped into common address space

I just got a hobby of studying this topic and it is quite intriguing. In one of the books, I came up with the following question: A computing hardware is to be designed with a processor generating ...
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity

Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
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Words in computer's memory

I don't know much about memory. Here are some lines from CLRS: The words in a computer memory are typically addressed by integers from 0 to $M - 1$, where $M$ is a suitably large integer. In many ...
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What is the nature of the two bits of data held in a computer memory cell?

I hope this question doesn't offend anyone. I start off by saying that I have and always had difficulty understand the language used in computer science so I have to interpret everything into the ...
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Reading process memory of computer A on computer B?

So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
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What are address shadows?

In my uni lecture, I am covering address decoding. I understand that memory addresses are decoded to find if they point to the RAM, ROM, or I/O, by way of the address (in the example of BBC Micro) ...
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Difference between Sequential ,Direct and Random acess with their acess time

I'm stuck on a point while reading about these different accessing methods. As per author. Sequential access Memory is organized into units of data, called records.Access must be made in a ...
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Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Memory Controller Actions

Can a memory controller read from memory and send from memory simultaneously and is the main system bus involved in this reading from memory? I posted a question I still do not understand but this is ...
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Bus Bandwidth Calculations

I cannot understand this question and the model answer for it and I wonder if anyone here is able to help me. Question: ...
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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How does changing cache size and/or block size affect the hit rate of the for loops in the following code?

I am working on practice problems to study for an upcoming exam. I am given the following piece of code: ...
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What is the maximum memory address space that microprocessor can access directly if a 16-bit memory module is interfaced with a 32-bit microprocessor?

The Complete question is as follows : Consider a single-address 32-bit microprocessor with 32-bit address bus and 32-bit data bus. Its instructions composed of 1-byte opcode and 3-byte operand address....
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Virtual Memory - Calculating Page Table Size and Other Attributes

Im struggling to understand the answer to a question: Consider a system with 2MiB physical memory and 4GiB virtual memory. Page size is 4KiB. If we choose to store seven information bits in each PTE, ...
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The memory a page table occupies and finding the # of pages within it

Was doing some practice and saw this question: Assume we’re working on a machine which has the following parameters: • 16GiB of physical memory • 22 bit virtual addresses • 128B pages • Each PTE in ...
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Row Major Vs Column Major Order: 2D arrays access in programming languages

Programmers prefer accessing a 2D array in Row-Major Order rather than Column-Major Order, Why? Are there some advantages/benefits of accessing a 2D array in row-major as compare to column-major? ...
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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In a DBMS what are the implementation details that make set operations faster than cursors?

What are the low level implementation details that make set based operations exponentially faster than iterative processes, like cursors? At a memory level how does a set operation "touch" the data ...
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Finding upper bound on number of I/Os needed to generate all permutations of some input in external memory

The general approach outlined in this paper in its proof of the lower bound on the average number of I/Os needed to obtain a given permutation of some input in external memory is as follows. Note that ...
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Loading a word from byte-addressable cache

I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead.. So, my question is pretty much the same as the one in the question I ...
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Page fault rate while calculating effective access time

So here is a question regarding calculating effective access time (EAT). So the question is : suppose a system with an average page page-fault service time of 6 milliseconds and a memory access time ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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Segmented address / normal virtual address

In a cpu with segmented memory, can an address only be accessed with a segmented address, or can a normal virtual address also be used?
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Connection of different buses to memory

The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) ...
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Computer Architecture, Memory Interleaving. Decoding step can be interleaved?

A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ ...
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What is the Memory Bandwidth Usage in a Program Related to?

We can use performance counter tools to check the memory bandwidth usage while a program is running. I want to ask what is this memory bandwidth related to? What parameters are involved in memory ...
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Comparing Registers with 16-bits

I am given with this information: "CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=...
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How memory address decoders works?

I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube 4 is the input (address bus) and 16 is the output. 4 X 16 can only access 16 unique addresses. What if I have thousands of ...
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Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
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Cache effective access time calculation

In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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1answer
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Does weak consistency allow reordering of events?

I am on studying a consistency model: weak consistency. weak consistency This model was first defined by Dubois et al. (1986), by saying that it has three properties: Accesses to synchronization ...
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Storage in registers

Whenever CPU needs the data, it gives the address of that word to the RAM via bus, then the RAM generated the copy of that word and sends to the registers via bus. Why can't the RAM send the original ...
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How can a 16-bit or more processor store a byte in a byte-addressed memory

I am confused as to how a 16-bit (or 32, 64) processor can store multiple adjacent bytes at once without supplying multiple addresses For example say we have (16-bit processor) 0xABCD starting at ...
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Unbanked access, banked access and common memory access

What are they and what are their differences? Unbanked access Banked access Common memory access [EDIT] This question is originated from my reading of MPLAB XC8 PIC Assembler User's Guide where the ...
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
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How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
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What's the maximum memory address space that the processor can access directly if it connected to a 16-bit memory?

The question is the following: 3. Given a hypothetical microprocessor which generates a 16-bit address (assume that the program counter and address registers are 16 bits wide) and has a 16 bit data ...
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Efficiently storing and modifying a reorderable data structure in a database

I'm trying to create a list curation web app. One thing that's important to me is being able to drag-and-drop reorder items in the list easily. At first I thought I could just store the order of each ...
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Big-endian systems and the smallest memory address

I read on en.Wikipedia that "Big-endian systems store the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in ...
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CPU Registers and Computation

How exactly does the control unit in the CPU retrieves data from registers? Does it retrieve bit by bit? For example if I'm adding two numbers, A+B, how does the computation takes place in memory ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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How does a hard drive knows what bit is the beginning of of a byte/word?

I'm guessing I could replace the words "hard drive" with "random access medium" but let's be more specific here. Also for the sake of this question, let's not consider SSDs. Just plain old hard-drives ...
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Understanding memory leaks in C/C++ [closed]

I was looking at an example here: https://blog.parasoft.com/finding-memory-leaks-in-c ...