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When there's no memory, should malloc or read/write fail?

To my surprise, I recently found out that Windows would fail a large memory allocation even if little of said memory is to actually be used, e.g. even if you don't want the swap, you better not ...
cnst's user avatar
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Measuring Cache Access Time

I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them: ...
Agustín Núñez's user avatar
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1 answer
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
Sourajit's user avatar
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Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
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Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
committedandroider's user avatar
2 votes
1 answer
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Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
robotron's user avatar
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4 answers
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Difference between Sequential ,Direct and Random acess with their acess time

I'm stuck on a point while reading about these different accessing methods. As per author. Sequential access Memory is organized into units of data, called records.Access must be made in a ...
Nikhil Badyal's user avatar
1 vote
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474 views

How the data is transferred from main memory to hard disk?

I understand that data is transferred from the main memory to the CPU and vise versa using the data bus. But, I am unable to understand, how the data is being transferred from the main memory to the ...
Twinkle's user avatar
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Find offset and page number given paged virtual memory address

I ran into this question in class: Assume a machine that is 64-bit and has 8GB memory. They use a paged virtual memory where the page size is 4KB. You run the following program: ...
Melanie's user avatar
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How is readiness of instructions fetched from RAM signaled to the CPU?

In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the ...
Magnus's user avatar
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Minimising total access time to elements in an array which is accessed sequentially

Starting with two examples: for(i = 1; i<10; i++) {B[i] = 0;} for(i = 1; i<10; i++) {B[2i] = 0;} In the first example, ...
Iceberry's user avatar
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
Revoltechs's user avatar
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Addresses with no memory allocated

I've read that a program can crash if it tries to access addresses with no memory allocated. But, how is it possible that an address has no memory allocated? When does it happen?
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Disk Scheduling for a Fragmented Hard-Drive

Recently In class I have been learning about simple disk scheduling algorithms such as FCFS, STTF, LOOK, LOOK-SCAN etc. From my understanding these algorithms schedule I/O requests depending on which ...
Fady's user avatar
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Why is the method of im2col with GEMM is more efficient than the method of direction implementation with SIMD in CNN

The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement convolutional layers is to expand the image into a ...
Jogging Song's user avatar
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Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
Cyanidies's user avatar
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703 views

Dividing/Multiplying Numbers Stored in two memory locations

I have two numbers x and y. The upper bits of x are stored at location m, while the lower bits of x are stored at location n. The upper bits of y are stored at location i, while the lower bits of y ...
xfern's user avatar
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static paging vocabulary request

What is the term for an algorithm that always requests the same sequence of pages? I recall seeing this concept before but haven't been able to find anything on Google without more specific ...
SamM's user avatar
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Is there a delay between two commands to read data from RAM?

Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
Slaycapь's user avatar
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How hardware write a byte in memory?

I want to know how hardwares write a byte in memory? If there is difference between writing process in RAM and ROM I would like to know as well. Specially I want to know: Is hardware writes values ...
Khashayar's user avatar
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Performance of CPU with two caches

I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this Cache L1 ...
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Definition of the term "access efficiency" in the context of computer systems

In a two-level virtual memory, the memory access time for main memory, $t_M=10^{−8}$ sec, and the memory access time for the secondary memory, $t_D=10^{−3}$ sec. What must be the hit ratio, $H$ such ...
Abhishek Ghosh's user avatar
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2 answers
88 views

Select signals for memory mapped into common address space

I just got a hobby of studying this topic and it is quite intriguing. In one of the books, I came up with the following question: A computing hardware is to be designed with a processor generating ...
kiv's user avatar
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3 answers
1k views

Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
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How memory address decoders works?

I keep seeing 3 X 8, 4 X 16, etc. kind of decoders explained on youtube 4 is the input (address bus) and 16 is the output. 4 X 16 can only access 16 unique addresses. What if I have thousands of ...
Ken Kaneki's user avatar
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146 views

Unbanked access, banked access and common memory access

What are they and what are their differences? Unbanked access Banked access Common memory access [EDIT] This question is originated from my reading of MPLAB XC8 PIC Assembler User's Guide where the ...
KMC's user avatar
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2 answers
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Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
SanMu's user avatar
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
Vishal Sharma's user avatar
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243 views

Storing binary tree with arbitrarily sized nodes without linked-list or large 32-bit pointers

So you can store a binary tree without pointers using a 1-D array: Binary Trees can be represented using 1-D array in memory(Fig 1).The rule to store binary tree in array are : The values of ...
Lance's user avatar
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Understanding the notation and concept behind March Tests

Some background on my question: I have done some research into March Tests that are essentially access patterns for DRAM. One example of these march tests in the MATS+ algorithm shown below with (I ...
Jason McCullough's user avatar
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What happens when accessing 0x00ABBA?

Given the following page table with a 24 Bit virtual address and 4KB page size and 4 byte long entries (%X means hexadecimal values): I don't understand how to translate e.g. address %X00ABBA here. I ...
akihikokayaba's user avatar
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187 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
Thomas Lee's user avatar
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0 answers
396 views

What is the algorithmic complexity of DFS under the cache oblivious model?

Consider the basic non-recursive DFS algorithm on a graph G=(V,E) (python-like pseudocode below) that uses array-based adjacency lists, a couple of arrays of size V, and a dynamic array stack of size &...
Paulo's user avatar
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Fully associative cache - calculate address tag bits?

I have the following task: Main memory capacity = 64MB (B = byte) Cache capacity = 64KB Block size = 16B Processor addressed information with address A = 0052A622h Calculate address tag ...
Millkovac's user avatar
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0 answers
145 views

Calculating Unique Addresses In Word Addressable Memory

According to a textbook assigned for my class, if I have memory that is 4M X 16, to address this memory (assuming word addressing), we need to be able to uniquely identify $2^{12}$ different items, ...
AndrewSmiley's user avatar
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0 answers
742 views

How do you calculate when effective access time is greater than cache access time?

I'm having trouble understanding how to calculate effective access time, hit ratios and cache access times. I'm unfamiliar with the concepts and would love help, or an explanation on how to solve this ...
coracora's user avatar
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0 answers
420 views

Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
committedandroider's user avatar