Questions tagged [memory-access]
The memory-access tag has no usage guidance.
163
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How memory controller reads from RAM with O(1) time complexity?
I am trying to understand how a RAM memory controller gets data with instant access while reading through the memory. Let's say initially, ram gets the data at address 0 and then to get the data at ...
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Approximate cache size & cache line size from optimal tile size
I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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What's the maximum memory address space that the processor can access directly if it connected to a 16-bit memory?
The question is the following:
3. Given a hypothetical microprocessor which generates a 16-bit address (assume that the program counter and address registers are 16 bits wide) and has a 16 bit data ...
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Distinction between paging and segmentation?
In my operating systems textbook, there is a paragraph which states:
As for the contents of each PTE, we have a number of different bits
in there worth understanding at some level. A valid bit is ...
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Are all data structures in the von Neumann architecture based on the array, or array-like?
I am an old Pythonista now learning C and how various data structures and types are implemented, such as binary trees and hash tables. Learning about the latter, leads me understand that the hash ...
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Difference between Sequential ,Direct and Random acess with their acess time
I'm stuck on a point while reading about these different accessing methods. As per author.
Sequential access
Memory is organized into units of data, called records.Access must be made in a ...
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Byte addressable vs Word addressable
I am trying to understand the difference between byte addressing and word addressing.
A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The ...
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Understanding memory mapping conceptually
I've already read several blogs and questions on stack exchange, but I'm unable to grasp what the real drawbacks of memory mapped files are. I see the following are frequently listed:
You can't ...
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In a DBMS what are the implementation details that make set operations faster than cursors?
What are the low level implementation details that make set based operations exponentially faster than iterative processes, like cursors?
At a memory level how does a set operation "touch" the data ...
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Clarification on interplay between cache line size and read/write sizes
Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes.
According to my understanding, we use a number ...
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How does the memory of a 64bit and 32bit processor work
In this article, the author states that a 64bit processor can theoretically reference 2^64 bytes of memory. What does he mean by this statement, or rather the word, reference?
Also, I visualize the ...
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Memory interfacing problem [duplicate]
I've learnt that the memory interfacing problem is used when we need to connect a memory that has lesser number of locations to a processor that has more address lines.
For eg. Connecting memory chips ...
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578
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Address and data bus
When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about?
Also, why is the address bus unidirectional, as opposed to the data bus?
...
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Why don't integer multiplication algorithms use lookup tables?
It seems to me that we can use lookup tables for multiplication of two integers of size $\log(n)/2$, and that the number of entries for each table of these numbers should be $O(n)$.
Now, multiplying ...
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Addresses with no memory allocated
I've read that a program can crash if it tries to access addresses with no memory allocated. But, how is it possible that an address has no memory allocated? When does it happen?
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Finding size of cache in blocks
Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5
Now, in the solution it says
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Storing binary tree with arbitrarily sized nodes without linked-list or large 32-bit pointers
So you can store a binary tree without pointers using a 1-D array:
Binary Trees can be represented using 1-D array in memory(Fig 1).The rule to store binary tree in array are :
The values of ...
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Memory Mapping Segment
I read that "Memory Mapping Segment"/"memory mapped file" is a segment of the virtual memory of a process, where a file or file-like Ressource is loaded into. It is for high performance file I/O.
I ...
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jump to MMIO address
In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)?
Would this ...
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Disk Scheduling for a Fragmented Hard-Drive
Recently In class I have been learning about simple disk scheduling algorithms such as FCFS, STTF, LOOK, LOOK-SCAN etc. From my understanding these algorithms schedule I/O requests depending on which ...
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How to find percentage of CPU time consumed during DMA operation?
Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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Registers in a CPU
https://en.wikipedia.org/wiki/Processor_register
So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
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Architecture - calculating miss penalty
I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty
If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) ...
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Cache effective access time calculation
In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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what is the meaning of hit time?
Average memory access time = Hit time + Miss rate * miss penalty
Assume a computer with only one cache level. What is the exact meaning of hit time? Is it the ...
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Why is the method of im2col with GEMM is more efficient than the method of direction implementation with SIMD in CNN
The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement
convolutional layers is to expand the image into a ...
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Loading a word from byte-addressable cache
I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead..
So, my question is pretty much the same as the one in the question I ...
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accessing out of range physical address
What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
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AMAT calculation
I was just solving an exercise when the answer of this suprised me :
We have a memory hierarchy built with 2 levels of caches and a main memory, the access time of the L1 is 1 cycle, for L2 it's 10 ...
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Valid bit incoherence between TLB and Page Table
In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
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How does cache partitioning prevent covert/side-channel attacks?
In a report on an open-source separation kernel (Muen kernel) I was reading,
in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks.
It is ...
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How does RAMDAC get notified about framebuffer write?
I'm learning computer graphics, and I read this course lecture in order to understand how graphics I/O works under the hood. But the following explanation was not very clear to me:
The values in ...
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Linked List fundamental concepts [closed]
I am trying to understand the basics of Linked List. The definition of my LinkedList class is as follows:
...
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Question on "Hitting the memory wall, implications of the obvious"
I'm reading through a short paper about hitting the memory wall and I'm struggling to understand how exactly said wall will be hit.
The equation for average access time is fairly simple ...
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How can a 16-bit or more processor store a byte in a byte-addressed memory
I am confused as to how a 16-bit (or 32, 64) processor can store multiple adjacent bytes at once without supplying multiple addresses
For example say we have (16-bit processor) 0xABCD starting at ...
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Understanding the notation and concept behind March Tests
Some background on my question:
I have done some research into March Tests that are essentially access patterns for DRAM.
One example of these march tests in the MATS+ algorithm shown below with (I ...
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103
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How should I "read" a dereference operator?
For example, when I look at some code like
int x = 1;
int * y = &x;
I can read it like
...
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Seek time and latency on disc for a file that is stored sequentially?
Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
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Does having more bus in the computer increasing speed? [closed]
Whát i mention here is for having 2x bus will increasing 2x memory access speed like 3x will have 3x memory access speed like that !
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Cache efficient matrix multiplication
Consider these matrices:
$A=\begin{bmatrix}1 & 2\\3 & 4\end{bmatrix}$
$B=\begin{bmatrix}-1 & -2\\-3 & -4\end{bmatrix}$
Using standard algorithm:
$C=\begin{bmatrix}1*-1+2*-3 & 1*...
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Why sequential access is faster than random access?
I am currently getting really confused of two documents I read:
one is from Wikipedia that states:
The opposite is sequential access, where a remote element takes longer time to access.
and this ...
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If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?
Let's say we are working with a system that has 40 physical address bits. The total physical address space (assuming byte-addressable memory) is $2^{40}$ bytes, or 1 TiB. And if virtual addresses are ...
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How do Hard Drives Send and Recieve Data?
Ok. I know this is probably a commonly asked question. Before you refer me to a site or answer this yourself, I ask for you to please read this through. I have been into computers and electronics for ...
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Exactly why the time taken by 'memory reads', is not considered while calculating time complexity of an algorithm?
I am sorry if I sound repetitive(I've asked a similar sounding question earlier - Relevance of memory reads while calculating the time complexity of an algorithm). Actually, it didn't answered my ...
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What happens when accessing 0x00ABBA?
Given the following page table with a 24 Bit virtual address and 4KB page size and 4 byte long entries (%X means hexadecimal values):
I don't understand how to translate e.g. address %X00ABBA here. I ...
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Relevance of memory reads while calculating the time complexity of an algorithm
Can there be a genuine algorithm in which number of memory reads far outnumber the
no. of operations performed? For example, number of memory reads scale with n^2, while no. of operations scale with ...
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How is segmentation different from multiprogramming with fixed partition?
As seen here:
It works same like multiprogramming with fixed partition and also the memory is contiguous as well. How is it different and especially non-contiguous? What's happening here?
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Since physical memory is the RAM where is logical memory stored on the computer?
Since logical memory maps to the RAM (physical memory) it has be stored somewhere right and it will obviously take large bunch of memory of itself. Where is it stored?
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Calculating fractions of accesses from various levels of memory? (L2 - Main)
I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer.
The question goes;
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Row Major Vs Column Major Order: 2D arrays access in programming languages
Programmers prefer accessing a 2D array in Row-Major Order rather than Column-Major Order, Why?
Are there some advantages/benefits of accessing a 2D array in row-major as compare to column-major?
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