Questions tagged [memory-access]

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Direct-mapping cache

I had this question on a previous homework assignment and was unable to answer it. I've done some research and am not really able to find anything that clears this up for me. Would appreciate any help ...
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Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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260 views

What is the algorithmic complexity of DFS under the cache oblivious model?

Consider the basic non-recursive DFS algorithm on a graph G=(V,E) (python-like pseudocode below) that uses array-based adjacency lists, a couple of arrays of size V, and a dynamic array stack of size &...
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5answers
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How do computers remember where they store things?

When a computer stores a variable, when a program needs to get the variable's value, how does the computer know where to look in memory for that variable's value?
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2answers
7k views

How does RAM is shared in multi core environment?

I learnt that multi core processors have more than one processing units( i.e. the main executing units ALU etc.) and they are better at performance. I want to know how they share Physical memory. I'll ...
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295 views

Fully associative cache - calculate address tag bits?

I have the following task: Main memory capacity = 64MB (B = byte) Cache capacity = 64KB Block size = 16B Processor addressed information with address A = 0052A622h Calculate address tag ...
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2answers
617 views

Understanding non-faulting and faulting software prefetches

What is the difference between a faulting and non-faulting software prefetch. I have read some material in Google but can't understand it deeply. How do we know if a software prefetch is faulting or ...
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3answers
1k views

Does word addressable memory have more bytes than byte addressable memory?

Well, my question - if word addressable memory has more bytes than byte addressable memory - is derived from the fact that in word addressable memory each address addresses a word and in byte ...
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1answer
101 views

Fundamental idea of this memory denial of service simulation using array copy?

I am just watching this lecture Computer Organization - Introduction And Basics where the lecturer mentions about using a simple code to demonstrate how memory denial of service can be simulated in ...
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3answers
539 views

What are some “easy” unreasonable implications of O(1) time memory access?

If you are given a memory address $n$ bits long, then you need to at least process those bits. Hence, if you have $N$ memory available, addressed by $n$ bits, it would take $O(\mathbf{log}(N)) = O(n)$...
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1answer
608 views

What is an addressable cell size?

This question started with a quiz question from my university: Consider a big-endian computer system with an addressable cell size of one byte. The values in memory cells 372 to 375 are shown in the ...
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2answers
5k views

How does CPU actually retrieve data from memory when you call a variable in a programming language?

As I have understood from all the internet sources I can get to, when you declare and initialize a variable in java, you are allocating this data, say an 8-byte float, in a particular memory cell in ...
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1answer
45 views

Mapping several memories to one address space

I am trying to understand deeply how memories work in computers, and I faced the next difficulty. Let's say we have a device with two memory chips but only one address space (for example, 0x00000000 ...
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Calculating Unique Addresses In Word Addressable Memory

According to a textbook assigned for my class, if I have memory that is 4M X 16, to address this memory (assuming word addressing), we need to be able to uniquely identify $2^{12}$ different items, ...
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1answer
6k views

what is the difference between memory access and data memory access?

what is the difference between memory access and data memory access? for example, here are the examples of register transfer language instructions: $R1 ←[18]$ $R2 ←[R1 +3]$ $R1 ← R1 +...
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1answer
6k views

What is M referring to when talking about memory size( 4M x 8)

In the following paragraph its talking about memory and it throws M into the L X W of memory notation and i'm confused on how 4M = 2^22. Thanks in advance PARAGRAPH: Memory is built from random ...
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1answer
862 views

How can I calculate the effective bandwidth of a memory system?

I am currently doing my homework for my Computer Architecture class. One of the questions asks: A computer has a 64-bit data bus and 64-bit-wide memory blocks. The memory devices have an access ...
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6k views

Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
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3answers
721 views

How does a hard drive knows what bit is the beginning of of a byte/word?

I'm guessing I could replace the words "hard drive" with "random access medium" but let's be more specific here. Also for the sake of this question, let's not consider SSDs. Just plain old hard-drives ...
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712 views

How do you calculate when effective access time is greater than cache access time?

I'm having trouble understanding how to calculate effective access time, hit ratios and cache access times. I'm unfamiliar with the concepts and would love help, or an explanation on how to solve this ...
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How does a computer determine the data type of a byte?

For example, if the computer has 10111100 stored on one particular byte of RAM, how does the computer know to interpret this byte as an integer, ASCII character, or ...
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0answers
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Dividing/Multiplying Numbers Stored in two memory locations

I have two numbers x and y. The upper bits of x are stored at location m, while the lower bits of x are stored at location n. The upper bits of y are stored at location i, while the lower bits of y ...
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2answers
471 views

Bytes and bits conversion?

It is claimed in my textbook that In a 32-bit system, The instruction LDR r4,[r6] lets you address a logical space of 4GB. I know where the 4GB comes from, It is simply 2^32 / (1024 x 1024 x ...
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1answer
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How does the operating system set up memory boundaries? [closed]

Is there a hardware interrupt that is pre-configured by the OS or something? Try to keep the answer on the scale of a register or so. Are some special preparatory signals sent across the bridges ...
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1answer
556 views

CPU reading cycles. [closed]

Assume the CPU has 64 data lines. Then Z reading cycles will be needed to load an array of 12 double-precision floating-point numbers, each number coded in eight bytes, from the main memory into the ...
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1answer
1k views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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1answer
868 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
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0answers
2k views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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1answer
9k views

Would it be possible to use the cloud for RAM?

I'm not sure if this is the right place to ask but I had this idea. Since the cloud can be used for storing memory, would it be possible to use it for RAM too?
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When there's no memory, should malloc or read/write fail?

To my surprise, I recently found out that Windows would fail a large memory allocation even if little of said memory is to actually be used, e.g. even if you don't want the swap, you better not ...
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2answers
890 views

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
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1answer
55 views

Computing vector load and stores [closed]

If $a,b,c,y$ are all scalar doubles, then $y = a\cdot b$ would result in 16 bytes from loading $a,b$ and 8 bytes for storing $y$, a total of 24 bytes transferred. Likewise, $y = a\cdot b + c$ results ...
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Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
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2answers
8k views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, 10 ...
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1answer
809 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
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3answers
2k views

Is order of bits in byte really not of concern?

What I can't wrap my head around is sentence repeated everywhere I look, that order of bits in byte is not important(not of my, as a programmer, concern). My question then is if there is possibility ...
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1answer
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What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
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1answer
2k views

Comparing random access and sequential access

Assume that we choose randomly $k$ distinct numbers $N_1$, $\dots$, $N_k$ in $\{1, \dots, k\}$ and we have a file of $k$ parts. We have these two cases : We read (or write) sequentially from part $1$ ...
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2answers
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How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
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Maximum memory accessible by the CPU [closed]

I've read multiple times (for example in some of the answers to this question https://stackoverflow.com/questions/8869563/how-much-memory-can-be-accessed-by-a-32-bit-machine) that a CPU with 32 bit ...
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2answers
2k views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
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4answers
12k views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
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5answers
23k views

How to determine the maximum RAM capacity for an operating system?

I was curious to know what limits the max RAM capacity for an OS while reading about microprocessors being 32-bit and 64-bit. I know that limit for 32-bit OS is 4GB and for 64-bit OS is 16 Exabytes, ...
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1answer
861 views

How to determine the address of an element in a square matrix given the base address? [closed]

I was asked this question in examination. A square matrix $M$ of size $10 \times 10$ is stored in memory with each element requiring 4 bytes of storage. If the base address at $M[0][0]$ is $1840$, ...
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1answer
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Valid-invalid bit in a process page table

Valid-invalid bit is used to indicate whether a page in a process’s page table is valid or not. Why is it needed? Does that mean that each page table has a certain minimum size, i.e. it can ...
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2answers
298 views

Valgrind: what is the difference between a store and a modify? [closed]

I am using the Vlagrind lackey tool to examine the full memory reference string of a running computer program and wonder what the difference between a "store" and a "modify" might be - and do these ...
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1answer
62 views

Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
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1answer
594 views

DFA memory bandwidth

When we talk about DFA, we say that each new character from the input requires one memory access. What does that mean? This is what I think about this. Please tell me is this right? For example, I ...
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0answers
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static paging vocabulary request

What is the term for an algorithm that always requests the same sequence of pages? I recall seeing this concept before but haven't been able to find anything on Google without more specific ...