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If the current memory location is 2^6 then what will happen if we give full jump i.e 2^28

Each machine cycle executes one machine instruction.At the top of machinr cycle the pc contains address of ab instruction to fetch from memory.The instruction is fetch into the processor and is ...
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20 views

How the software was first time introduced to the hardware?

I often thought that when the software is devoloped for the very first time then how we introduced it to the hardware that this is a software to run.I asked it to many people but did not satisfy.
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21 views

How does the system know how to read the correct block from a disk?

I am watching this video (https://www.youtube.com/watch?v=aZjYr87r1b8) and up to the ~6 minute mark, he explains the disk structure and how when you want to read a block, the spinner spins to the ...
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Are memcomputing and neuromorphic computing the same thing?

As the title reads, I’m just trying to understand if there is any difference between memcomputing and neuromorphic computing. If so, what are they? Memcomputing: https://www.popularmechanics.com/...
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12 views

ROM in Computer and Mobile [closed]

why in computer, ROM is BIOS not HDD but in mobile ROM is Internal storage which is like HDD
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14 views

Why Does The Division Alorithim Need [Register Size] + 1 Iterations

Following this flow diagram for division hardware I made a program to "simulate" division on $N^+$. ...
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1answer
63 views

accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
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21 views

Fast MMU Emulation

How could one implement a MMU (memory mapping unit) on a CPU with coarser control than the target and have it be fast? Let's say the host has a 4K page size and the guest a 1K page size. I have ...
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23 views

How does DDR3 & DDR4 memory interact with the cache? What are the differences?

I looked up how these two protocols work, but I could not find any legitimate sources. Please provide any if you know. Thanks!
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1answer
52 views

Is the spigot algorithm for $\pi$ useful for computing all the digits of $\pi$?

I'm asking the question here because it's not a purely mathematical question and the answer also depends on how computers work. I think that according to the Wikipedia article Bailey–Borwein–Plouffe ...
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18 views

What are the approaches to private computations?

I'm talking about the ability to safely run a virtual machine on a physical device that is not trusted. It is necessary that the owner can not access the data that the virtual machine operates on. I ...
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1answer
23 views

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
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1answer
29 views

What the heck is a memory channel “CS bus”?

While I was reading about memory architecture from the CMSC 22200's Lecture 17 of University of Chicago, I got stuck on determining the meaning of the word "CS" used for describing a bus as part of ...
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1answer
24 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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93 views

Why is rotational latency usually not considered in disk scheduling?

I was pondering upon this question and couldn't get a satisfactory answer from my TA. I searched it up and here's what it showed: Most disks do not export their rotational position information to ...
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1answer
29 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
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128 views

Basic examples of static and dynamic RAM

What could be the basic examples (or the one that we are familiar of) of static and dynamic RAM? My Thoughts: First of all $\color{RED}{\text{RAM}}$ is something whose contents will be lost if ...
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1answer
139 views

how does cpu read 32 bit word from memory

I'm interested in how does cpu read 32 bit word from memory .If the processor has 32 bits of address space then it can address 4,294,967,295 locations (or 4 gb) Does this mean that each location ...
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2answers
304 views

Representation of used space and free space in hard drives

I've read from this How data is physically stored in hard drives, that the North/South orientation of the magnetic medium represents data as 0 or 1 physically in the hard drive. Data is stored in ...
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34 views

How can an 8-bit computer have a 20-bit address bus?

I'm in the middle of building a homemade processor from logic chips, and I've been trying to figure out how I can have RAM (for main memory) and ROM (for small booting stuff) on the bus at the same ...
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1answer
727 views

Why RAID 2 would ever be used instead of RAID 3?

According to this source and Tanenbaum's Modern Operating Systems a possible implementation of RAID 2 consists of 4 data disks and 3 disks which contain parity bits. Why don't we need 4 disks that ...
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0answers
20 views

Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
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1answer
29 views

Does having more bus in the computer increasing speed? [closed]

Whát i mention here is for having 2x bus will increasing 2x memory access speed like 3x will have 3x memory access speed like that !
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334 views

how to calculate cache size?

How do you calculate the cache size for direct mapping, and does it in anyway differ from associative mapping For example: Let's say you have a byte-addressable main memory of 4 Mbytes, block sizes ...
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36 views

GPUs where each core has dedicated local memory

Is there a processor chip with at least 500 MHz clock that has at least 100 cores such that the local memory for each core is dedicated to that core and has at least a few megabytes of RAM per core. ...
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72 views

How is there a CPU read misses on exclusive caches?

If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive. It is exclusive because it is only there. How can there be ...
3
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1answer
224 views

Variable size and CPU performance

When you learn programming they tell you choose data types that suffice for the concepts you're expressing, i.e. not too small because then your data won't fit and not too big because you don't want ...
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1answer
359 views

Signed and Unsigned Loads in a 32-bit Registers

I have a question over this quote directly out of Computer Organization and Design, 5e: Signed versus unsigned applies to loads as well as to arithmetic. The function of a signed load is to copy ...
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2answers
262 views

How do Hard Drives Send and Recieve Data?

Ok. I know this is probably a commonly asked question. Before you refer me to a site or answer this yourself, I ask for you to please read this through. I have been into computers and electronics for ...
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24 views

Should we consider number of surfaces in a disk while calculating effective data transfer rate?

Suppose a disk has Number of surfaces: 8 Number of sectors per track: 20 Sector size: 4000B Number of tracks: 10 It is rotating at 360 rpm. So disk is reading data from one track at an instance....
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1answer
82 views

RAM and the degrees of freedom

This question is about computation/computational physics. Imagine that you want to solve $10^6$ equations of motion, and you have $10^6$ degrees of freedom (position of the particle). How many RAM ...
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2answers
331 views

Why page size = size of one cache way?

Why is that the page size equals the size of one cache way? My book states "A direct-mapped cache cannot be bigger than a page".
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2answers
74 views

How many bytes of memory is used just to “acknowledge” that a certain file is a .jpg?

I'm rather new to computers and how they work in the microscopic scale, but here's the little bit that I know. Computers have lots of transistors in them, both in memory and processor, and each ...
2
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1answer
47 views

What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
0
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1answer
114 views

how one memory can be accessed simultaneously in instruction fetch and data read?

In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel. But datas and instructions are usually in same memory, and their access address is ...
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1answer
53 views

What does one mean by addressing capability of a microprocessor?

I read in a book that the Intel 80286 microprocessor has an addressing capability of 16 MB. Does this mean it can process 16 MB of data at a time? Please explain what is actually meant by addressing ...
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2answers
1k views

1 bit register with data flip flop doesn't store bit?

A 1-bit register: Credit: Elements of Computing Systems by Noam Nisan and Shimon Schocken ISBN-13: 978-0262640688 I know that the data flip flop outputs the input at the previous time step. ...
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3answers
77 views

A question on instruction executing speed

I am new to computer science, so excuse me if the question is inappropriate or sounds absurd to you. In the textbook, it says that a typical laptop can execute 1 billion instructions per second. ...
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2answers
238 views

What's the difference between Memory Byte (Mb) and Mega Byte (mb) [closed]

I am currently running my head around to understand if i am actually getting it correct or not? A memory chip with 1 byte cell size has 12 address lines. How many data lines does the chip have? What ...
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0answers
86 views

What's the current cost of SRAM? [closed]

I'm teaching Architecture this semester, and I'm using Computer Organization and Design (Patterson & Hennessy) as the text. The book contains a table that has the typical access time and cost of ...
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2answers
2k views

What is the relation between word size and size of internal register of a processor?

Is there any difference between word size and size of internal register of CPU ,since "Word size" refers to the number of bits processed by a computer's CPU in one go ,so does this imply that word ...
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0answers
25 views

Hardware Transactional Memory Operations in a Hyperthreaded Core

If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other ...
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2answers
184 views

I am a little bit confused about how to calculate the memory capacity

I am a little bit confused about how to calculate the memory capacity. word=data lines size byte=8 bit n=adresse lines size Most of the people use this formula ...
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1answer
90 views

Less used data (1 byte) in memory address holding 4 bytes [closed]

I need to store two distinct variables of 1 byte size in memory. My memory system stores 4 bytes at one address; therefore, you cannot address byte 3 directly, and you have to logically access it ...
3
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1answer
40 views

Can bar codes theoretically be considered a type of digital memory?

Bar codes act just like any other device that contains data that you can read from. Can bar codes thus be considered a type of computer memory? I believe the principle is quite similar to the optical ...
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0answers
82 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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1answer
155 views

Why register access bandwidth is higher then residing inside CPU cache?

Access to registers claimed to be faster then cache. Why is it? Is it because cache has less wires or spatially further from functional units?
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1answer
821 views

Basic question about 4-way set associative

When the CPU writes or reads from the memory and stores the value that was read or written into L1 cache. Do the CPU store the whole block( 1 block , leaves the other three ways empty) or the whole ...
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3answers
633 views

Does word addressable memory have more bytes than byte addressable memory?

Well, my question - if word addressable memory has more bytes than byte addressable memory - is derived from the fact that in word addressable memory each address addresses a word and in byte ...
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17 views

Advice on using DRAMSimm2 or other DRAM simulation tools

As part of my PhD research I am currently building a simulation of a 256 core NoC and really want to model its interaction with the memory system. My supervisor has suggested using the University of ...