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Questions tagged [memory-hardware]

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RAM architecture vs. CPU architecture

I have learned that initially PCs had 8-bit memory architecture and that 1 byte (i.e. 8 bits) was the "basic" memory unit because 8 bits was exactly the memory space required to encode any ...
Jan Stuller's user avatar
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Is memory barrier NECESSARY for memory consistency?

After reading Memory Barriers: a Hardware View for Software Hackers, I came up with a point which I am not sure of its correctness, as posted in the title. I came up with this point because of ...
Xavier Z.'s user avatar
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Why is ROM read only? And why do SSDs use it?

I was researching about SSDs and ended up going further and reading about how it uses flash technology which from what I gather is pretty much an EEPROM, which (I might be wrong on this) is just an ...
WaveCave's user avatar
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Inverting position of MMU and cache inside a computer

I was thinking about a topic in my actual course and a question came to my mind. What would happen if, at the hardware level, the position of the MMU and the cache were reversed inside a computer? ...
AndJ's user avatar
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Are modern ram architectures (DDR4 or SDRAM) Multi-port or Dual-port?

So I recently learned about dual-port and multi-port RAM but I tried doing some research on modern RAM architectures and if they use it but I couldn't find anything on it.
Cookie Infinity's user avatar
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Why do two pairs of identical DDR4 RAM not work together?

Several years ago, I tried to get two identical pairs of DDR4 RAM to run together in my computer. I have since bought a set of four, but I've always wondered why the RAM didn't work. Its been long ...
Sam Chamberlain's user avatar
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1 answer
54 views

How CPU uses wider address bus than register size?

i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). ...
piotrek's user avatar
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What could cause a Windows 11 machine to have so much more elapsed time relative to a Windows 10 machine?

I have a Windows 10 desktop (6 years old - Dell Optiplex) and a new Windows 11 laptop (maybe last years model - Lenovo Thinkpad P16 Gen2). I am running scripts in R to compare their compute times. The ...
jdods's user avatar
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The Atlas system word addresses

I'm reading about the Atlas operating system and I came across this: The Atlas system used a British computer with 48-bit words. Addresses were 24 bits but were encoded in decimal, which allowed 1 ...
beginwithc's user avatar
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How does virtualization handle modern TLBs?

In an answer to this question: For instance, modern Intel TLBs have a process context ID (PCID); each TLB entry is tagged with the PCID of the process that the page mapping is for, and the processor ...
whoisit's user avatar
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Cache Miss in First Private Cache but Hit in Shared LEvel 2 Cache: Does it Result in a Penalty?

In the context of Shared Memory Multiprocessor (SMP) systems with different cache levels, if a cache miss occurs in the first private cache but is followed by a hit in the second shared cache, would ...
First_1st's user avatar
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Why when calculating how long it would take to read a file from a harddrive do I not use transfer speed per sector?

I'm working on a problem from my textbook (not homework, just an example), and it asks us to calculate the 'best case' scenario of reading a 1MB file from the hard drive. I don't know why the right ...
PerformingAlbatross's user avatar
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1 answer
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Same Address and Write signal for two block of RAM?

I don't know if I asked the question in correct way but I will try to explain what's the thing I am not getting. I am currently reading book titled "Code: The Hidden Language of Computer Hardware ...
izack's user avatar
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If the register size and the address bus are equal so do we need those segementation register to segment our memory?

In 8086, as i know we need those segementation register to segment our memory because the address bus is 20 bit and register size is 16. So, If the register size and the address bus are equal and we ...
Mahmoud Basha's user avatar
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Memory Address Block diagram

Given A memory chip that has 4-addresses and each address location holds 8-bits is denoted as (4×8) RAM chip. I want to draw a block-diagram showing the memory address that the first 3 chips will hold ...
mathCOMPSCI's user avatar
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Understanding the Relationship Between CPU Registers Amounts and Maximum RAM in 32-bit Architectures

To my knowledge, The number of CPU registers can tell us the maximum RAM we can have. I am only talking about physical memory, no virtual memory or virtualization in my question. A 32-bit CPU ...
Ahmad Addas's user avatar
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At what precision are GPT's parameters stored?

OpenAI's technical paper on GPT-3 says that GPT-3 has 175 billion parameters. Several sites (here, here) claim that these parameters are stored as single-precision floating-point numbers and so ...
tparker's user avatar
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Physical memory address space

When you address physical memory, in the kernel, is it just another value like 0xf78f9 just like virtual addresses (and the only thing that is different is that the ...
user129393192's user avatar
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1 answer
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Disk addressing

I am wondering how disk addresses are accessed from a program. From my understanding, the two main facilities are programmed I/O (instructions) and memory-mapped I/O (simply loads and stores). The ...
user129393192's user avatar
2 votes
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Log-Structured Filesystem -- why do we need an explicit, scattered inode map?

From OSTEP Chp. 43: The imap is a structure that takes an inode number as input and produces the disk address of the most recent version of the inode This makes sense to me as a solution to the ...
user129393192's user avatar
1 vote
1 answer
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How does non-DMA transfers really work?

I recently discussed DMA and non-DMA with my OS professor. Here is my current understanding: disk controller has its own CPU, maybe own ISA, tiny program that simply handles reading from the disk (...
user129393192's user avatar
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How are memory busses and capacity determined?

If m = Ram quantity in GB, b = bus width in bits, and n = a nonnegative integer, it appears that b = m•2^n and or m = w/2^n, what do the variables represent physically? I.e., what physically changes ...
Sam Levi's user avatar
3 votes
0 answers
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k-compact vectored I/O

I have a practical programming problem that I am struggling to find an optimal algorithm for, in part because I don't know what to call it. The problem concerns vectored I/O (scatter/gather). Consider ...
George Hodgkins's user avatar
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1 answer
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How is the memory address structured when the number of blocks per cache set is not a power of 2?

When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization: $$Address = TAG|...
Ramzi Baaguigui's user avatar
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3 answers
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Why does a 32 bit address only contain 1 byte, when 32 bits = 4 bytes?

I am really confused about it. I think 32 bits = 4 bytes but 32 bit address is only 1 bit.
ABC's user avatar
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1 vote
2 answers
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Does the OS come in the hard drive?

This might be a a simple and for some a silly question as well. If I buy two hard drives and have windows in one and Ubuntu in the other, can I work with both two systems(one at a time). Example, I ...
ThunderGlove's user avatar
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1 answer
53 views

Is there any reason why you cannot use flash memory for a hard disk?

Is there a reason why you cannot use flash memory as a HD? Less moving parts and more affordable. Whats not to like? Why dont we see Pci-express cards with a couple of terrabytes of flash memory that ...
Neil Meyer's user avatar
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2 answers
531 views

How many bits are needed to reference physical vs virtual addresses?

I trying to learn about virtual memory at the moment and one of the explanations I've look at has a diagram like below. You can see that 32 bit virtual addresses are used so the virtual address space ...
jaduuuui's user avatar
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2 answers
150 views

Are variables stored again in RAM?

Assuming this set of instructions: declare variable 'A' which has value 5 declare variable 'B' which has value 2 From what I've understood, those instructions are loaded into RAM an then read by CPU,...
Marshall's user avatar
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0 answers
55 views

Memory Hierarchy Mappings to real world

This article from IBM (link) talks about Memory hierarchy in its actual hardware parts. NUMA While operating systems present memory to the running applications as a unified space, modern large ...
isomorphik's user avatar
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1 answer
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How can computers tell where the beginning and end of file/packet/frame headers are?

I'd like to know how a computer can determine the beginning and end of certain file components (attributes, headers, frame/packet/segment headers etc.) when these components can be omitted or added in ...
Inquisitive's user avatar
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0 answers
54 views

How hardware write a byte in memory?

I want to know how hardwares write a byte in memory? If there is difference between writing process in RAM and ROM I would like to know as well. Specially I want to know: Is hardware writes values ...
Khashayar's user avatar
0 votes
2 answers
218 views

Are all CPU computations done using registers?

From my understanding, a CPU register is a temporary storage or working location built into the CPU itself. The CPU includes some functional units such as the ALU (which is part of the chip, as far as ...
wrongbyte's user avatar
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Single port register file

I have a test that asks to build a register file using only a single port. The register file should also output 2 values, the read values, and be able to write one. I tried to build it, but ,simply ...
eojpyd's user avatar
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Is it possible to directly access permanently deleted data from SSD without recovering it using recovery program?

Is any technique present in this technical world regarding accessing data directly from any type of storing device without recovery it. For example if I deleted permanently data and then want to ...
Pritam kumar's user avatar
1 vote
0 answers
12 views

Why place of MA in MB then copy from MB to IR rather than going straight from MA to IR

During the fetch stage of the fetch-execute cycle, why are the contents of the cell whose address is in the MA (memory address register) placed in MB (memory buffer) then copied to IR (instruction ...
amroman's user avatar
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0 votes
1 answer
107 views

Max RAM capacity on modern cpus

I am wondering why modern consumer cpu usually has 128GB memory limit when server cpu supports terabytes. 128GB is really not that much. Do they really can't handle more RAM? How wide is their address ...
T k's user avatar
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0 answers
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Why PRAM and not PROM?

I read: NVRAM is the updated Mac terminology for PRAM and is short for Non-Volatile RAM. Plus, I know that there are 2 types of main memory RAM and ROM while the first is Volatile the second isn't. ...
daniel's user avatar
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0 votes
2 answers
201 views

Logical vs physical address program loaded into RAM, how re-mapping done?

What are common primary mechanisms to "re-map" between physical memory in RAM, and the addresses used in a program before it is loaded into RAM? In image below for example, the LOAD 12 ...
Guest's user avatar
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0 answers
573 views

Calculate memory size given address and its value

Given the address 00011001111011101111101011011111 and it save a value 0x1FA0CBB7. Calculate the memory size in KB What i try: the address has 32 bits so the memory size is 2^32 = 4294967296 bytes ...
Huỳnh Nguyễn Ngọc Hải's user avatar
0 votes
1 answer
105 views

Are sample memory access traces/dumps available, and where?

I am looking for a realistic physical memory access trace/dump of significant, but not insane, length (on the order of 1M accesses) for the purpose of cache simulation. Preferably for a 16-bit or 32-...
DYZ's user avatar
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3 votes
1 answer
114 views

What is the nature of the two bits of data held in a computer memory cell?

I hope this question doesn't offend anyone. I start off by saying that I have and always had difficulty understand the language used in computer science so I have to interpret everything into the ...
Meta_Alchemy's user avatar
2 votes
1 answer
341 views

How LRU is used without special hardware?

I had been curious as to which page replacement algorithm is used in OSes like Windows and Linux. I could find that most information on the internet pointed at LRU(Least Recently Used) Algorithm. But ...
Yuv's user avatar
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2 votes
1 answer
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How does software prefetching work with in order processors?

From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching: ...
Rufat Imanov's user avatar
0 votes
2 answers
265 views

Are the number of entries in the TLB(Translation Lookaside Buffer) limited?

If not, then why aren't all the pages loaded into the TLB so that TLB misses never happen.
Yuv's user avatar
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1 vote
1 answer
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Assembly Language Step By Step: Why deviate from the norm and design computers where the presence of voltage encodes a 0 bit?

That the presence of voltage across a switch encodes 12 is purely arbitrary... Jeff Duntemann's book mentions: We could as well have said that the lack of voltage indicates a binary 1 and vice versa (...
puwlah's user avatar
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1 vote
1 answer
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Is RAM always volatile? [closed]

I understand that computer memory in typical modern computing systems (such as the laptop I am asking this question from) is generally involatile but in some exceptions, such as RAM, the memory is ...
RAMOS's user avatar
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0 votes
2 answers
308 views

can a computer be totally made up of SRAM?

can a computer be totally made up of SRAM with no DRAM but with secondary memory and run an opreating system properly?
jd singh's user avatar
1 vote
0 answers
47 views

What does "Memory of 128K by 9" means?

This is probably a very stupid question but I couldn't find an answer anywhere. I'm reading the Technical Reference book of the IBM PC XT and it says that "The system board also has from 128K by ...
Djann's user avatar
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1 vote
1 answer
66 views

How can computer memory remember after the computer runs out of battery?

According to my fragile knowledge of computer hardware the way computers store information is by electric circuits. If there is current the bit is 1 if there isnt its 0. My question is after a ...
sean python's user avatar

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