Questions tagged [memory-hardware]

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Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?

I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
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37 views

Slowdown when accessing data at page boundaries?

Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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1answer
65 views

Why is 2^32 in a 32-bit system = 4GiB and not 4Gib?

I was watching this video 32-Bit vs 64-Bit - The Advantage and at 1:19 (timestamp) the narrator mentioned the 4GB memory allocation for the 32-bit system. I later found out it should've been 4GiB but ...
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Without Rare Metals [closed]

One often sees assertions that these are "necessary" for modern military and consumer computing applications. I presume that without these rare metals, the devices could be manufactured, but would be ...
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Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
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State-machine semantics of instruction set architectures

An instruction set architecture is an abstraction, a common interface layer between the software and the micro-architecture. The existence of this clearly delineated interface is becoming increasingly ...
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How does the memory of a 64bit and 32bit processor work

In this article, the author states that a 64bit processor can theoretically reference 2^64 bytes of memory. What does he mean by this statement, or rather the word, reference? Also, I visualize the ...
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Why do we still use a Von Neumann Architecture in modern computers?

The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons. To this day the Von Neumann ...
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Memory addressing

What does the following sentence mean? "The 8085 micropressor has the capability of addressing 64KB of RAM?" In general, what is the meaning of a CPU's ability to address a given amount of memory? ...
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Address bus and memory

If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it? What I'm trying to ask is that do all the 65536 locations ...
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1answer
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Address and data bus

When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about? Also, why is the address bus unidirectional, as opposed to the data bus? ...
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1answer
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Importance of Frequency vs CAS Latency in memory performance

I was looking at the Wikipedia page for CAS Latency: https://en.wikipedia.org/wiki/CAS_latency And I noticed the obvious trend - at higher frequency, despite CAS latency degrading (growing), the ...
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Difference between RAM and buffer

I have searched but didn't get any exact difference between RAM and a buffer. If both are used for temporary storage, then why they are named differently while both having same property?
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Address of the Last Byte of Installed Memory

I'm a university student currently taking an Assembly and Computer Organization class. On last weeks lab we were given a question: Suppose that you buy a 32bit PC with 16 MB of Ram. What is the 8-hex-...
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How n-queens problem can see in VLSI testing?

I am doing project with n-queens problem.I have found n-queens can be used in VLSI testing.How it can be applied in VLSI testing?
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ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
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1answer
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jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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1answer
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No. of disk blocks writes required for writing the file

Assume that a file is written using write(fd, buf, K) system calls, where fd is the file descriptor, and K, the number of files to be written to the current file offset which is a multiple of the disk ...
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What happens when a file is being moved/copied to another location at the same hard drive?

I've got a few questions about how hard-drives works with information that I haven't been able to find the answers to anywhere, so I figured I'd give this a shot instead. I know the basics on how ...
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How Does an Operating System/BIOS Determine Physical Addresses of Devices?

So I understand that in every computer, the Operating System, the BIOS, or both will determine the physical addresses of the hardware devices and then translate that into virtual addresses. What I don'...
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How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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1answer
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Registers in a CPU

https://en.wikipedia.org/wiki/Processor_register So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
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Is memory possible without a flip flop circuit?

All the memory circuits I've seen use some form of flip-flop/feedback mechanism to store a value. Is this the only circuit design that can store a value?
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1answer
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How does the system know how to read the correct block from a disk?

I am watching this video (https://www.youtube.com/watch?v=aZjYr87r1b8) and up to the ~6 minute mark, he explains the disk structure and how when you want to read a block, the spinner spins to the ...
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Are memcomputing and neuromorphic computing the same thing?

As the title reads, I’m just trying to understand if there is any difference between memcomputing and neuromorphic computing. If so, what are they? Memcomputing: https://www.popularmechanics.com/...
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Why Does The Division Alorithim Need [Register Size] + 1 Iterations

Following this flow diagram for division hardware I made a program to "simulate" division on $N^+$. ...
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1answer
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accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
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Is the spigot algorithm for $\pi$ useful for computing all the digits of $\pi$?

I'm asking the question here because it's not a purely mathematical question and the answer also depends on how computers work. I think that according to the Wikipedia article Bailey–Borwein–Plouffe ...
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What are the approaches to private computations?

I'm talking about the ability to safely run a virtual machine on a physical device that is not trusted. It is necessary that the owner can not access the data that the virtual machine operates on. I ...
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1answer
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How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
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What the heck is a memory channel “CS bus”?

While I was reading about memory architecture from the CMSC 22200's Lecture 17 of University of Chicago, I got stuck on determining the meaning of the word "CS" used for describing a bus as part of ...
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1answer
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DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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1answer
154 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
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Basic examples of static and dynamic RAM

What could be the basic examples (or the one that we are familiar of) of static and dynamic RAM? My Thoughts: First of all $\color{RED}{\text{RAM}}$ is something whose contents will be lost if ...
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how does cpu read 32 bit word from memory

I'm interested in how does cpu read 32 bit word from memory .If the processor has 32 bits of address space then it can address 4,294,967,295 locations (or 4 gb) Does this mean that each location ...
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Representation of used space and free space in hard drives

I've read from this How data is physically stored in hard drives, that the North/South orientation of the magnetic medium represents data as 0 or 1 physically in the hard drive. Data is stored in ...
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How can an 8-bit computer have a 20-bit address bus?

I'm in the middle of building a homemade processor from logic chips, and I've been trying to figure out how I can have RAM (for main memory) and ROM (for small booting stuff) on the bus at the same ...
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1answer
964 views

Why RAID 2 would ever be used instead of RAID 3?

According to this source and Tanenbaum's Modern Operating Systems a possible implementation of RAID 2 consists of 4 data disks and 3 disks which contain parity bits. Why don't we need 4 disks that ...
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Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
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Does having more bus in the computer increasing speed? [closed]

Whát i mention here is for having 2x bus will increasing 2x memory access speed like 3x will have 3x memory access speed like that !
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How is there a CPU read misses on exclusive caches?

If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive. It is exclusive because it is only there. How can there be ...
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1answer
480 views

Variable size and CPU performance

When you learn programming they tell you choose data types that suffice for the concepts you're expressing, i.e. not too small because then your data won't fit and not too big because you don't want ...
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1answer
585 views

Signed and Unsigned Loads in a 32-bit Registers

I have a question over this quote directly out of Computer Organization and Design, 5e: Signed versus unsigned applies to loads as well as to arithmetic. The function of a signed load is to copy ...
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2answers
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How do Hard Drives Send and Recieve Data?

Ok. I know this is probably a commonly asked question. Before you refer me to a site or answer this yourself, I ask for you to please read this through. I have been into computers and electronics for ...
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Should we consider number of surfaces in a disk while calculating effective data transfer rate?

Suppose a disk has Number of surfaces: 8 Number of sectors per track: 20 Sector size: 4000B Number of tracks: 10 It is rotating at 360 rpm. So disk is reading data from one track at an instance....
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1answer
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RAM and the degrees of freedom

This question is about computation/computational physics. Imagine that you want to solve $10^6$ equations of motion, and you have $10^6$ degrees of freedom (position of the particle). How many RAM ...
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Why page size = size of one cache way?

Why is that the page size equals the size of one cache way? My book states "A direct-mapped cache cannot be bigger than a page".
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How many bytes of memory is used just to “acknowledge” that a certain file is a .jpg?

I'm rather new to computers and how they work in the microscopic scale, but here's the little bit that I know. Computers have lots of transistors in them, both in memory and processor, and each ...
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What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
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how one memory can be accessed simultaneously in instruction fetch and data read?

In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel. But datas and instructions are usually in same memory, and their access address is ...