Questions tagged [memory-hardware]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
2
votes
1answer
28 views

Optimal encoding scheme for semi-rewritable memory?

Let's define a "semi-rewritable" memory device as having the following properties: The initial blank media is initialised with all zeroes. When writing to the media, individual zeroes can ...
0
votes
1answer
79 views

Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
0
votes
0answers
17 views

Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
0
votes
1answer
79 views

Would it be possible for a new technology to make RAM obsolete?

If a new technology is invented for storage devices, which is the same as or speeder than RAM (bandwidth&lanecy), is it possible to make RAM obsolete and consider the storage device as the main ...
28
votes
3answers
8k views

Why is the Nintendo Entertainment System (NES) referred to as an 8-bit system, rather than a 1-byte system?

As far as I've understood it, referring to this system as an 8-bit system points out that one can access 8 bits of data in one instruction. While I understand that we're not saving vast amounts of ...
0
votes
0answers
16 views

How does software interact with the cpu in the fetch execute cycle?

As the question suggests, is there any interaction or relationships between any sort of software and the cpu during the fetch-execute cycle?
1
vote
1answer
131 views

Finding number of memory locations in chip

I was solving some old MCQs and found this question: A RAM chip has 7 address lines, 8 data lines and 2 chip select lines. Then the number of memory locations is _____. (A) $2^{12}$ (B) $2^{10}$ (C) $...
1
vote
3answers
98 views

The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ? a)...
5
votes
1answer
268 views

Why is memory one dimensional?

Addresses in system programming languages like C are one dimensional (i.e. one number). This forces the programmer to make a decision whether matrices are stored "row major" or "column major" causing ...
1
vote
1answer
51 views

How does the hardware of a while loop work?

I know get how logical operators for if logic gates work, but I am trying to understand how while loops fit into that picture. I realize that this question is a bit vague. It all started because I was ...
1
vote
2answers
64 views

What other instructions are stored in the ROM?

Apart from the start-up instructions, what other programs are stored in the ROM?
0
votes
0answers
19 views

Names of circuits that comprise memory

I just had a quick question about memory, and I was looking to get some insight. I'm a student, and one of our homework questions was "name two circuits aside from memory cells that RAM must contain ...
0
votes
1answer
55 views

Can a 32-bit processor work with a 64-bit size word?

In a 32-bit byte addressable memory system, each "row" has 4 bytes and each byte has a 32-bit address. My question is: can I read and/or write word of length 64 bits from/to memory? In other terms, ...
2
votes
1answer
60 views

How memory controller reads from RAM with O(1) time complexity?

I am trying to understand how a RAM memory controller gets data with instant access while reading through the memory. Let's say initially, ram gets the data at address 0 and then to get the data at ...
2
votes
1answer
33 views

How does a dual core microprocessors run so many programs?

I have a laptop with Intel dual core and it runs, the OS windows, and many application from Opera, age of empires, word, excel etc open at once just fine. If it only has 2 cores, how can so many ...
0
votes
1answer
61 views

Distinction between paging and segmentation?

In my operating systems textbook, there is a paragraph which states: As for the contents of each PTE, we have a number of different bits in there worth understanding at some level. A valid bit is ...
0
votes
1answer
100 views

Who invented the adder, full-adder, half-adder?

I didn't find, in the digital design books, who invented the adders. The same person invented the half-adder and the full-adder? What's the oldest publication on digital arithmetic design?
1
vote
0answers
50 views

L1 Cache Missing Timing Attack

I'm trying to understand Section 3: L1 Cache Missing in the paper Cache Missing for Fun and Profit. I'm stuck on trying to figure out how the covert channel is ...
2
votes
1answer
121 views

Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?

I'm creating a simple row buffer simulator to go along with a simple cache simulator in order to count hits and misses in the row buffer. Whenever a cache block isn't in the cache I want to go look ...
1
vote
1answer
47 views

Slowdown when accessing data at page boundaries?

Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
2
votes
1answer
184 views

Why is 2^32 in a 32-bit system = 4GiB and not 4Gib?

I was watching this video 32-Bit vs 64-Bit - The Advantage and at 1:19 (timestamp) the narrator mentioned the 4GB memory allocation for the 32-bit system. I later found out it should've been 4GiB but ...
0
votes
2answers
89 views

Without Rare Metals [closed]

One often sees assertions that these are "necessary" for modern military and consumer computing applications. I presume that without these rare metals, the devices could be manufactured, but would be ...
0
votes
3answers
360 views

Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
0
votes
2answers
57 views

How does the memory of a 64bit and 32bit processor work

In this article, the author states that a 64bit processor can theoretically reference 2^64 bytes of memory. What does he mean by this statement, or rather the word, reference? Also, I visualize the ...
2
votes
3answers
1k views

Why do we still use a Von Neumann Architecture in modern computers?

The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons. To this day the Von Neumann ...
0
votes
2answers
234 views

Address bus and memory

If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it? What I'm trying to ask is that do all the 65536 locations ...
1
vote
1answer
140 views

Address and data bus

When people use the word "bidirectional" while describing buses, what are the two "directions" that are being talked about? Also, why is the address bus unidirectional, as opposed to the data bus? ...
0
votes
2answers
156 views

Importance of Frequency vs CAS Latency in memory performance

I was looking at the Wikipedia page for CAS Latency: https://en.wikipedia.org/wiki/CAS_latency And I noticed the obvious trend - at higher frequency, despite CAS latency degrading (growing), the ...
3
votes
3answers
2k views

Difference between RAM and buffer

I have searched but didn't get any exact difference between RAM and a buffer. If both are used for temporary storage, then why they are named differently while both having same property?
1
vote
0answers
186 views

Address of the Last Byte of Installed Memory

I'm a university student currently taking an Assembly and Computer Organization class. On last weeks lab we were given a question: Suppose that you buy a 32bit PC with 16 MB of Ram. What is the 8-hex-...
0
votes
1answer
68 views

ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
0
votes
1answer
49 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
0
votes
1answer
28 views

No. of disk blocks writes required for writing the file

Assume that a file is written using write(fd, buf, K) system calls, where fd is the file descriptor, and K, the number of files to be written to the current file offset which is a multiple of the disk ...
1
vote
0answers
17 views

What happens when a file is being moved/copied to another location at the same hard drive?

I've got a few questions about how hard-drives works with information that I haven't been able to find the answers to anywhere, so I figured I'd give this a shot instead. I know the basics on how ...
0
votes
0answers
22 views

How Does an Operating System/BIOS Determine Physical Addresses of Devices?

So I understand that in every computer, the Operating System, the BIOS, or both will determine the physical addresses of the hardware devices and then translate that into virtual addresses. What I don'...
0
votes
1answer
441 views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
1
vote
1answer
33 views

Registers in a CPU

https://en.wikipedia.org/wiki/Processor_register So from the information in this link there are limited Floating point and General Purpose registers in a cpu. My question is how are these registers ...
0
votes
1answer
27 views

How does the system know how to read the correct block from a disk?

I am watching this video (https://www.youtube.com/watch?v=aZjYr87r1b8) and up to the ~6 minute mark, he explains the disk structure and how when you want to read a block, the spinner spins to the ...
2
votes
0answers
17 views

Are memcomputing and neuromorphic computing the same thing?

As the title reads, I’m just trying to understand if there is any difference between memcomputing and neuromorphic computing. If so, what are they? Memcomputing: https://www.popularmechanics.com/...
1
vote
1answer
32 views

Why Does The Division Alorithim Need [Register Size] + 1 Iterations

Following this flow diagram for division hardware I made a program to "simulate" division on $N^+$. ...
1
vote
1answer
106 views

accessing out of range physical address

What happens if a CPU instruction (e.g. on ARM architecture) tries to access a physical address that is out of range. This easily could happen if the CPU is on non-virtual (non-paging) mode. This ...
0
votes
1answer
196 views

Is the spigot algorithm for $\pi$ useful for computing all the digits of $\pi$?

I'm asking the question here because it's not a purely mathematical question and the answer also depends on how computers work. I think that according to the Wikipedia article Bailey–Borwein–Plouffe ...
1
vote
0answers
18 views

What are the approaches to private computations?

I'm talking about the ability to safely run a virtual machine on a physical device that is not trusted. It is necessary that the owner can not access the data that the virtual machine operates on. I ...
5
votes
1answer
75 views

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
0
votes
1answer
166 views

What the heck is a memory channel “CS bus”?

While I was reading about memory architecture from the CMSC 22200's Lecture 17 of University of Chicago, I got stuck on determining the meaning of the word "CS" used for describing a bus as part of ...
1
vote
1answer
38 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
1
vote
1answer
371 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
0
votes
0answers
1k views

Basic examples of static and dynamic RAM

What could be the basic examples (or the one that we are familiar of) of static and dynamic RAM? My Thoughts: First of all $\color{RED}{\text{RAM}}$ is something whose contents will be lost if ...
0
votes
1answer
466 views

how does cpu read 32 bit word from memory

I'm interested in how does cpu read 32 bit word from memory .If the processor has 32 bits of address space then it can address 4,294,967,295 locations (or 4 gb) Does this mean that each location ...
3
votes
2answers
312 views

Representation of used space and free space in hard drives

I've read from this How data is physically stored in hard drives, that the North/South orientation of the magnetic medium represents data as 0 or 1 physically in the hard drive. Data is stored in ...