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How does DDR3 & DDR4 memory interact with the cache? What are the differences?

I looked up how these two protocols work, but I could not find any legitimate sources. Please provide any if you know. Thanks!
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1answer
46 views

Is the spigot algorithm for $\pi$ useful for computing all the digits of $\pi$?

I'm asking the question here because it's not a purely mathematical question and the answer also depends on how computers work. I think that according to the Wikipedia article Bailey–Borwein–Plouffe ...
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0answers
18 views

What are the approaches to private computations?

I'm talking about the ability to safely run a virtual machine on a physical device that is not trusted. It is necessary that the owner can not access the data that the virtual machine operates on. I ...
4
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1answer
22 views

How does cache partitioning prevent covert/side-channel attacks?

In a report on an open-source separation kernel (Muen kernel) I was reading, in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks. It is ...
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1answer
27 views

What the heck is a memory channel “CS bus”?

While I was reading about memory architecture from the CMSC 22200's Lecture 17 of University of Chicago, I got stuck on determining the meaning of the word "CS" used for describing a bus as part of ...
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1answer
22 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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0answers
48 views

Why is rotational latency usually not considered in disk scheduling?

I was pondering upon this question and couldn't get a satisfactory answer from my TA. I searched it up and here's what it showed: Most disks do not export their rotational position information to ...
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1answer
26 views

Is finding cache size possible with information given?

An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set. A) What is the size of the cache in bytes? ...
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0answers
55 views

Basic examples of static and dynamic RAM

What could be the basic examples (or the one that we are familiar of) of static and dynamic RAM? My Thoughts: First of all $\color{RED}{\text{RAM}}$ is something whose contents will be lost if ...
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1answer
111 views

how does cpu read 32 bit word from memory

I'm interested in how does cpu read 32 bit word from memory .If the processor has 32 bits of address space then it can address 4,294,967,295 locations (or 4 gb) Does this mean that each location ...
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2answers
303 views

Representation of used space and free space in hard drives

I've read from this How data is physically stored in hard drives, that the North/South orientation of the magnetic medium represents data as 0 or 1 physically in the hard drive. Data is stored in ...
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28 views

How can an 8-bit computer have a 20-bit address bus?

I'm in the middle of building a homemade processor from logic chips, and I've been trying to figure out how I can have RAM (for main memory) and ROM (for small booting stuff) on the bus at the same ...
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1answer
693 views

Why RAID 2 would ever be used instead of RAID 3?

According to this source and Tanenbaum's Modern Operating Systems a possible implementation of RAID 2 consists of 4 data disks and 3 disks which contain parity bits. Why don't we need 4 disks that ...
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0answers
18 views

Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
0
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1answer
29 views

Does having more bus in the computer increasing speed? [closed]

Whát i mention here is for having 2x bus will increasing 2x memory access speed like 3x will have 3x memory access speed like that !
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0answers
299 views

how to calculate cache size?

How do you calculate the cache size for direct mapping, and does it in anyway differ from associative mapping For example: Let's say you have a byte-addressable main memory of 4 Mbytes, block sizes ...
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0answers
32 views

GPUs where each core has dedicated local memory

Is there a processor chip with at least 500 MHz clock that has at least 100 cores such that the local memory for each core is dedicated to that core and has at least a few megabytes of RAM per core. ...
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0answers
54 views

How is there a CPU read misses on exclusive caches?

If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive. It is exclusive because it is only there. How can there be ...
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0answers
20 views

Flynn's taxonomy, SWAR and visualising how it works?

I am familiar with Flynn's taxonomy, however, I can never properly visualise how some certain parts of it work. You may find it funny that I need to 'visualise' it somehow, but I do suffer from a ...
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0answers
21 views

What would be a mathematical rigorous definition of a memory address space?

What is the exact definition of a memory address space? Is it correct to name the set of all the numbers from 0 to the highest addressable byte the definition of an address space?
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1answer
174 views

Variable size and CPU performance

When you learn programming they tell you choose data types that suffice for the concepts you're expressing, i.e. not too small because then your data won't fit and not too big because you don't want ...
1
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1answer
272 views

Signed and Unsigned Loads in a 32-bit Registers

I have a question over this quote directly out of Computer Organization and Design, 5e: Signed versus unsigned applies to loads as well as to arithmetic. The function of a signed load is to copy ...
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2answers
260 views

How do Hard Drives Send and Recieve Data?

Ok. I know this is probably a commonly asked question. Before you refer me to a site or answer this yourself, I ask for you to please read this through. I have been into computers and electronics for ...
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0answers
23 views

Should we consider number of surfaces in a disk while calculating effective data transfer rate?

Suppose a disk has Number of surfaces: 8 Number of sectors per track: 20 Sector size: 4000B Number of tracks: 10 It is rotating at 360 rpm. So disk is reading data from one track at an instance....
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1answer
82 views

RAM and the degrees of freedom

This question is about computation/computational physics. Imagine that you want to solve $10^6$ equations of motion, and you have $10^6$ degrees of freedom (position of the particle). How many RAM ...
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2answers
282 views

Why page size = size of one cache way?

Why is that the page size equals the size of one cache way? My book states "A direct-mapped cache cannot be bigger than a page".
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2answers
73 views

How many bytes of memory is used just to “acknowledge” that a certain file is a .jpg?

I'm rather new to computers and how they work in the microscopic scale, but here's the little bit that I know. Computers have lots of transistors in them, both in memory and processor, and each ...
2
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1answer
43 views

What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
0
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1answer
80 views

how one memory can be accessed simultaneously in instruction fetch and data read?

In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel. But datas and instructions are usually in same memory, and their access address is ...
1
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1answer
49 views

What does one mean by addressing capability of a microprocessor?

I read in a book that the Intel 80286 microprocessor has an addressing capability of 16 MB. Does this mean it can process 16 MB of data at a time? Please explain what is actually meant by addressing ...
0
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2answers
948 views

1 bit register with data flip flop doesn't store bit?

A 1-bit register: Credit: Elements of Computing Systems by Noam Nisan and Shimon Schocken ISBN-13: 978-0262640688 I know that the data flip flop outputs the input at the previous time step. ...
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3answers
77 views

A question on instruction executing speed

I am new to computer science, so excuse me if the question is inappropriate or sounds absurd to you. In the textbook, it says that a typical laptop can execute 1 billion instructions per second. ...
-3
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2answers
208 views

What's the difference between Memory Byte (Mb) and Mega Byte (mb) [closed]

I am currently running my head around to understand if i am actually getting it correct or not? A memory chip with 1 byte cell size has 12 address lines. How many data lines does the chip have? What ...
3
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0answers
81 views

What's the current cost of SRAM? [closed]

I'm teaching Architecture this semester, and I'm using Computer Organization and Design (Patterson & Hennessy) as the text. The book contains a table that has the typical access time and cost of ...
1
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2answers
2k views

What is the relation between word size and size of internal register of a processor?

Is there any difference between word size and size of internal register of CPU ,since "Word size" refers to the number of bits processed by a computer's CPU in one go ,so does this imply that word ...
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0answers
25 views

Hardware Transactional Memory Operations in a Hyperthreaded Core

If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other ...
0
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2answers
146 views

I am a little bit confused about how to calculate the memory capacity

I am a little bit confused about how to calculate the memory capacity. word=data lines size byte=8 bit n=adresse lines size Most of the people use this formula ...
0
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1answer
85 views

Less used data (1 byte) in memory address holding 4 bytes [closed]

I need to store two distinct variables of 1 byte size in memory. My memory system stores 4 bytes at one address; therefore, you cannot address byte 3 directly, and you have to logically access it ...
3
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1answer
40 views

Can bar codes theoretically be considered a type of digital memory?

Bar codes act just like any other device that contains data that you can read from. Can bar codes thus be considered a type of computer memory? I believe the principle is quite similar to the optical ...
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0answers
61 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
0
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1answer
141 views

Why register access bandwidth is higher then residing inside CPU cache?

Access to registers claimed to be faster then cache. Why is it? Is it because cache has less wires or spatially further from functional units?
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1answer
736 views

Basic question about 4-way set associative

When the CPU writes or reads from the memory and stores the value that was read or written into L1 cache. Do the CPU store the whole block( 1 block , leaves the other three ways empty) or the whole ...
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3answers
541 views

Does word addressable memory have more bytes than byte addressable memory?

Well, my question - if word addressable memory has more bytes than byte addressable memory - is derived from the fact that in word addressable memory each address addresses a word and in byte ...
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0answers
17 views

Advice on using DRAMSimm2 or other DRAM simulation tools

As part of my PhD research I am currently building a simulation of a 256 core NoC and really want to model its interaction with the memory system. My supervisor has suggested using the University of ...
0
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2answers
220 views

Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
1
vote
1answer
666 views

How does the OS Scheduler give/take control of HW?

Imagine a uniprocessor system with a simple operating system with non-threaded processes and basic virtual memory (paging, no segmentation, no replacement to disk, etc). Now assume a simple ...
2
votes
1answer
90 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50) ...
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7answers
6k views

Is a computer without RAM, but with a disk, equivalent to one with RAM?

Memory is used for many things, as I understand. It serves as a disk-cache, and contains the programs' instructions, and their stack & heap. Here's a thought experiment. If one doesn't care about ...
1
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1answer
38 views

Mapping several memories to one address space

I am trying to understand deeply how memories work in computers, and I faced the next difficulty. Let's say we have a device with two memory chips but only one address space (for example, 0x00000000 ...
2
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1answer
68 views

How does a register remember value?

So I am studying this great book, and Chapter $3.1$ is about registers. Quoting from this book / chapter: A register is a storage device that can "store" or "remember" a value over time, ...