Questions tagged [memory-hardware]

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References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS kernels....
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Optimal encoding scheme for semi-rewritable memory?

Let's define a "semi-rewritable" memory device as having the following properties: The initial blank media is initialised with all zeroes. When writing to the media, individual zeroes can ...
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Are memcomputing and neuromorphic computing the same thing?

As the title reads, I’m just trying to understand if there is any difference between memcomputing and neuromorphic computing. If so, what are they? Memcomputing: https://www.popularmechanics.com/...
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How does the Spark M7 “Concurrent Fine-grain Memory Migration” benefit a garbage collector?

Sun has been making a lot of noise about the Spark M7 and its inbuilt support for the java garbage collector. However there seem to be very little easy to find information about it. Please can ...
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Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50) ...
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How are programs split up into pages in Memory Paging?

I am a bit confused about how the logical addresses are generated in a paging memory architecture and where and when a program is split up into pages. I understand how logical addresses are translated ...
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Is it reasonable to assume modern computers can do hardware math with integers up to 2^64?

I was writing up an algorithm that involved knowing the size of integers my hardware can manage without having to resort to software implementations of math operations and the additional computational ...
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Two Vs Dual Port RAM

Regarding the difference between Two Vs Dual Port RAM Here is what I understand: The first can read and write at the same time but can't read twice or read twice at the same time while the second can ...
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1answer
139 views

Hard Drive Seek Time using FIFO, SSF, SCAN

A hard disk spins at 6000 rpm (revolutions per minute), and it takes 100 μs (on average) for the head to traverse one track. Consider the following sequence of disk track requests: 27, 129, 110, 186, ...
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L1 Cache Missing Timing Attack

I'm trying to understand Section 3: L1 Cache Missing in the paper Cache Missing for Fun and Profit. I'm stuck on trying to figure out how the covert channel is ...
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278 views

Address of the Last Byte of Installed Memory

I'm a university student currently taking an Assembly and Computer Organization class. On last weeks lab we were given a question: Suppose that you buy a 32bit PC with 16 MB of Ram. What is the 8-hex-...
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What happens when a file is being moved/copied to another location at the same hard drive?

I've got a few questions about how hard-drives works with information that I haven't been able to find the answers to anywhere, so I figured I'd give this a shot instead. I know the basics on how ...
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650 views

How to find percentage of CPU time consumed during DMA operation?

Q) Consider 1MBps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred to main memory (1 word = 64 ...
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What are the approaches to private computations?

I'm talking about the ability to safely run a virtual machine on a physical device that is not trusted. It is necessary that the owner can not access the data that the virtual machine operates on. I ...
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Seek time and latency on disc for a file that is stored sequentially?

Say there is a file that is sequentially organized over 2.5 tracks on a disc. I'm assuming there would be a non-zero value for seek time and latency when accessing the first track, but what about the ...
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Hardware Transactional Memory Operations in a Hyperthreaded Core

If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other ...
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Drawing the Design of an SRAM chip

I have come across a question that I am having quite a hard time with. I am to draw a design of an SRAM chip with an organization of 2M*128 SRAM that uses 1K*1K arrays of D latches. And then the ...
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Reading process memory of computer A on computer B?

So I was wondering if there is a way of reading process memory of one device on another. So lets say a process is running on computer A, I then use some form of connection lan, pcie etc. Once the two ...
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how to calculate the speed of memory

I checked my Mac, it shows the memory is 16 GB 2400 Mhz, does it mean that the bandwidth is $ \dfrac{16\times1024}{8} \times 2400$, is there any thing wrong with that calculation, because the value ...
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Hardware implementation of direct mapped , set associative mapped and fully associative cache

I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
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Operations on row buffer in DRAM

I am trying to understand what is the hardware structure of the row buffer in the main memory. If there can be any shift operations or any other opeartions that can be made on the row buffer? Also, ...
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memory storage of a program before compiling

Whenever we write code, after compilation the code will be converted to machine language and then stored in the hard disk. But before compiling the code, it is still in the high-level language. How ...
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What bus DIMM (RAM module) uses?

I know there are different types of BUS like PCI, SCSI, ISA etc. What specific type of bus (for address bus and data bus) do a DIMM module use ?
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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How does software interact with the cpu in the fetch execute cycle?

As the question suggests, is there any interaction or relationships between any sort of software and the cpu during the fetch-execute cycle?
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Names of circuits that comprise memory

I just had a quick question about memory, and I was looking to get some insight. I'm a student, and one of our homework questions was "name two circuits aside from memory cells that RAM must contain ...
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How Does an Operating System/BIOS Determine Physical Addresses of Devices?

So I understand that in every computer, the Operating System, the BIOS, or both will determine the physical addresses of the hardware devices and then translate that into virtual addresses. What I don'...
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Basic examples of static and dynamic RAM

What could be the basic examples (or the one that we are familiar of) of static and dynamic RAM? My Thoughts: First of all $\color{RED}{\text{RAM}}$ is something whose contents will be lost if ...
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How can an 8-bit computer have a 20-bit address bus?

I'm in the middle of building a homemade processor from logic chips, and I've been trying to figure out how I can have RAM (for main memory) and ROM (for small booting stuff) on the bus at the same ...
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How is there a CPU read misses on exclusive caches?

If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive. It is exclusive because it is only there. How can there be ...
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Should we consider number of surfaces in a disk while calculating effective data transfer rate?

Suppose a disk has Number of surfaces: 8 Number of sectors per track: 20 Sector size: 4000B Number of tracks: 10 It is rotating at 360 rpm. So disk is reading data from one track at an instance....
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Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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Advice on using DRAMSimm2 or other DRAM simulation tools

As part of my PhD research I am currently building a simulation of a 256 core NoC and really want to model its interaction with the memory system. My supervisor has suggested using the University of ...
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Calculating Unique Addresses In Word Addressable Memory

According to a textbook assigned for my class, if I have memory that is 4M X 16, to address this memory (assuming word addressing), we need to be able to uniquely identify $2^{12}$ different items, ...
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Roles of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
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There should be some common piece of hardware /firmware or software among different devices, isn't it?

There should be some common piece of hardware /firmware or software among different devices, isn't it? like among PCs, PlayStation, Xbox, Android phones or feature phones from pre 2008 era etc. Is ...