Questions tagged [memory-hardware]

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What is the relation between word size and size of internal register of a processor?

Is there any difference between word size and size of internal register of CPU ,since "Word size" refers to the number of bits processed by a computer's CPU in one go ,so does this imply that word ...
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1answer
192 views

What is the basic idea behind the usage of TLBs?

I know how Translation Lookaside Buffers work, and i also know we use them to improve the performance of data/program access by storing the recent page numbers - frame numbers in a memory cache. The ...
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1answer
328 views

What does one mean by addressing capability of a microprocessor?

I read in a book that the Intel 80286 microprocessor has an addressing capability of 16 MB. Does this mean it can process 16 MB of data at a time? Please explain what is actually meant by addressing ...
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665 views

how one memory can be accessed simultaneously in instruction fetch and data read?

In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel. But datas and instructions are usually in same memory, and their access address is ...
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4k views

1 bit register with data flip flop doesn't store bit?

A 1-bit register: Credit: Elements of Computing Systems by Noam Nisan and Shimon Schocken ISBN-13: 978-0262640688 I know that the data flip flop outputs the input at the previous time step. ...
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3answers
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A question on instruction executing speed

I am new to computer science, so excuse me if the question is inappropriate or sounds absurd to you. In the textbook, it says that a typical laptop can execute 1 billion instructions per second. ...
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2answers
595 views

What's the difference between Memory Byte (Mb) and Mega Byte (mb) [closed]

I am currently running my head around to understand if i am actually getting it correct or not? A memory chip with 1 byte cell size has 12 address lines. How many data lines does the chip have? What ...
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3answers
1k views

Does word addressable memory have more bytes than byte addressable memory?

Well, my question - if word addressable memory has more bytes than byte addressable memory - is derived from the fact that in word addressable memory each address addresses a word and in byte ...
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0answers
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What's the current cost of SRAM? [closed]

I'm teaching Architecture this semester, and I'm using Computer Organization and Design (Patterson & Hennessy) as the text. The book contains a table that has the typical access time and cost of ...
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4answers
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Why do Computers use Hex Number System at assembly language?

Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? ...
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I am a little bit confused about how to calculate the memory capacity

I am a little bit confused about how to calculate the memory capacity. word=data lines size byte=8 bit n=adresse lines size Most of the people use this formula ...
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0answers
27 views

Hardware Transactional Memory Operations in a Hyperthreaded Core

If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other ...
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1answer
207 views

Less used data (1 byte) in memory address holding 4 bytes [closed]

I need to store two distinct variables of 1 byte size in memory. My memory system stores 4 bytes at one address; therefore, you cannot address byte 3 directly, and you have to logically access it ...
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1answer
68 views

Can bar codes theoretically be considered a type of digital memory?

Bar codes act just like any other device that contains data that you can read from. Can bar codes thus be considered a type of computer memory? I believe the principle is quite similar to the optical ...
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0answers
180 views

Direct Mapped Cache, textbook excerpt clarification, identifying block field

I have an excerpt from my textbook concerning direct mapped cache that I would like further clarification on, the text reads..... "Consider the following example: Assume memory consists of 2^14 ...
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1answer
319 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
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1answer
268 views

Why register access bandwidth is higher then residing inside CPU cache?

Access to registers claimed to be faster then cache. Why is it? Is it because cache has less wires or spatially further from functional units?
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1answer
1k views

Basic question about 4-way set associative

When the CPU writes or reads from the memory and stores the value that was read or written into L1 cache. Do the CPU store the whole block( 1 block , leaves the other three ways empty) or the whole ...
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Advice on using DRAMSimm2 or other DRAM simulation tools

As part of my PhD research I am currently building a simulation of a 256 core NoC and really want to model its interaction with the memory system. My supervisor has suggested using the University of ...
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1answer
634 views

How does hardware interrupt work on a physical layer

I'm a newbie in computer science and would to understand how hardware interrupts work at the physical layer. I ask my question considering a specific example. When packet arrives at the network ...
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1answer
132 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50) ...
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2answers
332 views

Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
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1answer
1k views

How does the OS Scheduler give/take control of HW?

Imagine a uniprocessor system with a simple operating system with non-threaded processes and basic virtual memory (paging, no segmentation, no replacement to disk, etc). Now assume a simple ...
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Is a computer without RAM, but with a disk, equivalent to one with RAM?

Memory is used for many things, as I understand. It serves as a disk-cache, and contains the programs' instructions, and their stack & heap. Here's a thought experiment. If one doesn't care about ...
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874 views

Why is word-addressable the exception, not the rule?

As stated on Wikipedia: Most modern computers are byte-addressable instead of word-addressable. Why is this case? Since the CPU processes words (of predominantly 64 bits or 8 bytes) now, wouldn't ...
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1answer
45 views

Mapping several memories to one address space

I am trying to understand deeply how memories work in computers, and I faced the next difficulty. Let's say we have a device with two memory chips but only one address space (for example, 0x00000000 ...
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1answer
107 views

How does a register remember value?

So I am studying this great book, and Chapter $3.1$ is about registers. Quoting from this book / chapter: A register is a storage device that can "store" or "remember" a value over time, ...
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82 views

Calculating Unique Addresses In Word Addressable Memory

According to a textbook assigned for my class, if I have memory that is 4M X 16, to address this memory (assuming word addressing), we need to be able to uniquely identify $2^{12}$ different items, ...
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1answer
1k views

Deleted data remains on a disk until? [closed]

I am little bit confused between the two answers below. What is the exact answer of this question? My query is, "Deleted data remains on a disk until...?" The data is overwritten; The recycle bin is ...
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2answers
115 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
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1answer
823 views

How can I calculate the effective bandwidth of a memory system?

I am currently doing my homework for my Computer Architecture class. One of the questions asks: A computer has a 64-bit data bus and 64-bit-wide memory blocks. The memory devices have an access ...
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0answers
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Would there be any advantage to using transitors of more than two states? [duplicate]

Binary is the result of using the simplest possible building blocks to hold memory, transistors, entities that can be switched between two states, on or off. We took that idea and ran with it, and it ...
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1answer
3k views

Relationship between RAM size and 32-bit vs 64-bit word size

I know that x86 supports only 4GB of RAM, and that switching to x64 greatly increases the size of RAM you can use, but I don't understand why. Why is the maximum supported ram size related to whether ...
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2answers
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/How/ is the machine code within the CPU physically implemented; /why/ precisely does this work; and /where/ is it stored? [closed]

I understand the concept that the CPU's machine code is what translates the binary input into commands, and then executes these commands, many billion times per second. I can understand how, given ...
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1answer
274 views

Where is the reorder buffer (ROB)? [closed]

I just wonder where the ROB is in. Is ROB in the memory or cache or where??
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2answers
72 views

Caches and reading a PDF

I am currently learning about caches in Systems class, and I had a few doubts about what exactly happens when a Computer reads a PDF. This is the sequence that happens in my mind: The CPU checks if ...
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2answers
580 views

What is a swap-with-memory instruction?

I am reading an article on algorithms for parallel computing and came across the following sentence. What do they mean by a swap-with-memory instruction? Our algorithm provides reasonable latency ...
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1answer
1k views

What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
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How does the Spark M7 “Concurrent Fine-grain Memory Migration” benefit a garbage collector?

Sun has been making a lot of noise about the Spark M7 and its inbuilt support for the java garbage collector. However there seem to be very little easy to find information about it. Please can ...
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79 views

References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS kernels....
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1answer
86 views

Cache question help me here? [closed]

Quantify the effect in performance which comes from using the cache ,if We are going to use a program which is made from 500 machine instructions ,from which 100 are in a cycle which is executed 25 ...
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1answer
406 views

RAW Data Hazard resolution

Let's consider the following MIPS (using pipelined arch.) assembly code: lw r1,0(r2) sub r4, r1, r6 and r6, r1, r7 or r8, r1, r9 the r1 value used in the second ...
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1answer
2k views

Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011

This is the problem I have: Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011 (2 pts.). In your solution, mark the parity bits as in the following example, where ...
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0answers
84 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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1answer
951 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
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2k views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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2answers
5k views

Advantage of byte addressable memory over word addressable memory

What is the reason that almost all computers (besides some DSPs) use byte addressable memory? With byte addressable memory and a 32 bit address you can have 4GB while with word addressable memory you ...
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2answers
866 views

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
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1answer
64 views

How is electricity brought to the transistors? [closed]

I feel like my knowledge of computer science is being hindered by this one concept. I understand the concepts of transistors and how a flow of electricity can turn a transistor on or off, and with ...
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3answers
5k views

How DMA improves I/O operation efficiency?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...