Questions tagged [memory-hierarchy]

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Computing miss penalty to L1 if block sizes are different in L1 and L2

I am having trouble computing the miss penalty in a L1 cache if the block size in L1 is different to the block size in L2 cache. Usually, miss penalty in L1 = hit time to L2 + (miss rate at L2) x (...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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LRU vs FIFO page replacement

I am wondering if there is an instance where FIFO results in less page faults than LRU. For example: 2,6,5,7... In this string, if I have to complete it by ...
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Calculating miss rate for 2 way set associative cache

From my homework: Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is ...
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How is an OS page stored in a k-way set-associative cache?

I have been reading about set-associative caches. As far as I have read, in case of n-way set-associative cache each way stores, a block (let's say 16 bytes) and therefore each set will be of size 16n ...