Questions tagged [mips]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
1 vote
1 answer
44 views

How can this MIPS processor execute one instruction in one cycle?

I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris. At the end of the section the autor shows this MIPS processor and ...
user avatar
0 votes
0 answers
22 views

Minimum bitrate of common bus (I/O system) with minimum delay

I have a 32-bit MIPS which is connected to the main memory and a I/O system which is related to memory-mapped I/O, while there is DMA controller. The I/O system has discrete I/O communication lines ...
user avatar
0 votes
1 answer
19 views

MIPS pipeline: MEM stage takes one cycle?

Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle: 1 cycle to read a register 4 cycles to reach to L1 cache 10 ...
user avatar
  • 143
1 vote
1 answer
49 views

Do number of registers and width of register have to be the same?

I am studying Computer Architecture with MIPS-32. The example system has 32 registers with each register having a width of 32 bit. If I would want 128 registers instead of 32 registers, would I have ...
user avatar
0 votes
1 answer
56 views

Why are lw and sw byte addressable but jump and beq word addressable?

I am refering to MIPS (32 bits). Is there any particular reason that when loading or storing a word, we address memory in bytes, but when we jump or branch using beq we address memory in words? Thanks!...
user avatar
0 votes
1 answer
69 views

Why does this branch data hazard happen during the instruction decode stage?

Suppose I have the following MIPS code on a CPU with forwarding enabled: ...
user avatar
  • 155
1 vote
0 answers
29 views

Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
user avatar
  • 111
0 votes
1 answer
412 views

Does higher cpi give better performance?

Does higher cpi give better performance? Lets say there is a code and we can run it by 3 methods. 1 cpi for single cycle 99 cpi for multi cycle 70 cpi for pipeline Multi cycle has the highest cpi for ...
user avatar
0 votes
1 answer
174 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
user avatar
0 votes
0 answers
36 views

Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
user avatar
1 vote
1 answer
543 views

Represent unsigned 12-bit octal numbers. Results in octal

I have an HW question where I found an answer that matches mine, but their breakdown confuses me. Ques: What is 4365 - 3412 when these values represent unsigned 12-bit octal numbers? The result should ...
user avatar
  • 11
1 vote
0 answers
171 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
user avatar
0 votes
0 answers
90 views

ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
user avatar
11 votes
3 answers
2k views

Are there competitions for integer programming?

Are there competitions for integer programming like there are for SAT and MAXSAT?
user avatar
2 votes
0 answers
27 views

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
user avatar
0 votes
1 answer
890 views

Why is the opcode 0 for all r-type instructions? Please explain your answer

I can't seem to find the explanation for why all r-type instructions have opcode 0 always. Can anybody explain why this is so.
user avatar
0 votes
2 answers
2k views

how pseudo direct addressing works?

In pseudo direct addressing mode (For the MIPS architecture) the 26 bit of the jump instruction are joined to the upper 4 bits of the PC . how could this help in jumping to relative positions suppose ...
user avatar
1 vote
1 answer
2k views

In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
user avatar
1 vote
1 answer
1k views

Data hazard after in load word after addi

5 stage pipline addi $t1,$zero,0x30 lw $t2,0($t1) sw $t2,0xff18($zero) addi $t2,$zero,100 Question is to find hazards existing in the code and the answer is:...
user avatar
  • 115
1 vote
0 answers
29 views

Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
user avatar
  • 11
0 votes
1 answer
458 views

Bytes addressable processor

In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
user avatar
  • 71
1 vote
1 answer
477 views

In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?

In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says Instruction fetch: The top portion of Figure 4.36 shows the instruction being read from ...
user avatar
1 vote
2 answers
1k views

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
user avatar
  • 111
0 votes
1 answer
378 views

Need help converting machine code

I would appreciate some help with this question. The 32 bit numbers below represent a MIPS instruction. identify the different fields and state which instruction it is. give the assembler source code ...
user avatar
  • 3
3 votes
1 answer
128 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
user avatar
  • 71
1 vote
1 answer
941 views

How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw $a0,...
user avatar
  • 153
1 vote
1 answer
82 views

Byte/word addressing

I am confused on byte addressable/word addressable architecture. I have studied MIPS implementation and I came to know that when the data is retrieved from main memory, it is shifted accordingly to ...
user avatar
  • 71
0 votes
1 answer
2k views

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
user avatar
  • 71
0 votes
1 answer
237 views

predication, branch prediction question

I have a question about predication and branch prediction. I've emailed my professor regarding this and he replied me that predication has a less instructions than branch prediction. So I tried ...
user avatar
3 votes
3 answers
629 views

Predication execution

I was studying branch prediction & predication execution and faced a trouble.. I'm not quite sure whether I understood the concept of predication but based on what I have learned it is taking ...
user avatar
1 vote
1 answer
4k views

How do I calculate Instruction Per Clock?

Hi! I faced a problem with calculating IPC. I can tell the answers were derived from IPC=instruction/number of cycles. But I have no idea why it has to be calculated that way. Just to understand ...
user avatar
0 votes
1 answer
4k views

MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion

I have question about the ALUOp control signal. When doing R type instructions, 31-26th bits are all 000000. What decides the instruction is actually the func field of 5-0th bits. In that case, I ...
user avatar
0 votes
1 answer
448 views

MIPS control signal table(R-type add)

I've been going through the control signal table and I noticed something confusing on when I should set the value as 'don't care' or 0 for control signal. For example when doing the R type add ...
user avatar
1 vote
0 answers
661 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
user avatar
  • 11
0 votes
1 answer
149 views

Computer Organization and Assembly Language Programming

Why do we need to learn MIPS Assembly language before learning computer organization? What are the implications of learning it first? As a computer scientist, why do we need to learn this one and ...
user avatar
  • 11
2 votes
0 answers
181 views

Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
user avatar
0 votes
2 answers
5k views

lw and sw hazards example MIPS

The below example confused me: lw $r0, 4($r0) sw $r0, 4($r0) add $r0, $r0, $r0 Using MIPS 5 stage execution what are the hazards we have 1) without forwarding 2) ...
user avatar
0 votes
0 answers
644 views

Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...
user avatar
  • 645