Questions tagged [mips]

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Data hazard in MIPS: SW after ADD

Use the five-stage pipeline with forwarding unit. add $t1, $t2, $t3 sw $t1, 0($t4) In the above code, is the data hazard of t1 fixed by forwarding the correct t1 ...
samli50801's user avatar
2 votes
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521 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
Abhishek Ghosh's user avatar
1 vote
1 answer
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Execution of instruction in MIPS on various parts of the clock cycle

I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
ronak jain's user avatar
1 vote
1 answer
57 views

Why does it have that amount of stalls

I'm doing an exercise about the MIPS pipeline with the following characteristics: -Branches and Branch targets are calculated in the E-stage. -There is forward logic from the output to the input of ...
begin's user avatar
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Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
Hoang Nam's user avatar
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Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
Ben's user avatar
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MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
HaiLe's user avatar
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Why can't I use data forwarding in this exercise?

as the title says, I am wondering why this exercise doesn't show a data forwarding from the "ex" stage of 2nd instruction to "ex" stage of 3rd instruction. P.S. the architecture is ...
unrealyozora's user avatar
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How do you determine the amount of bits for the tag, index, and offset in a MIPS byte-addressed direct-mapped cache when given only a list of address?

The question I'm working on is as follows: I'm still kind of working on how direct-mapped caches work in my computer organization class. I sort of understand that you need the least significant 2 ...
mrak-p's user avatar
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
Anshul Gupta's user avatar
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Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
noscreen's user avatar
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ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
John adams's user avatar
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660 views

Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...
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