Questions tagged [mips]

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12 votes
4 answers
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Are there competitions for integer programming?

Are there competitions for integer programming like there are for SAT and MAXSAT?
Omar Shehab's user avatar
3 votes
3 answers
898 views

Predication execution

I was studying branch prediction & predication execution and faced a trouble.. I'm not quite sure whether I understood the concept of predication but based on what I have learned it is taking ...
kyung sub Song's user avatar
3 votes
1 answer
163 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
Rajat's user avatar
  • 81
3 votes
1 answer
178 views

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
User9123's user avatar
2 votes
1 answer
45 views

Calculate the CPI of a program

...
First_1st's user avatar
2 votes
1 answer
200 views

Data hazard in MIPS: SW after ADD

Use the five-stage pipeline with forwarding unit. add $t1, $t2, $t3 sw $t1, 0($t4) In the above code, is the data hazard of t1 fixed by forwarding the correct t1 ...
samli50801's user avatar
2 votes
0 answers
521 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
Abhishek Ghosh's user avatar
2 votes
0 answers
200 views

Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
Promod Sampath Elvitigala's user avatar
1 vote
1 answer
567 views

Do number of registers and width of register have to be the same?

I am studying Computer Architecture with MIPS-32. The example system has 32 registers with each register having a width of 32 bit. If I would want 128 registers instead of 32 registers, would I have ...
curiouscupcake's user avatar
1 vote
1 answer
2k views

Why is the opcode 0 for all r-type instructions? Please explain your answer

I can't seem to find the explanation for why all r-type instructions have opcode 0 always. Can anybody explain why this is so.
jumpy123's user avatar
  • 101
1 vote
1 answer
87 views

MIPS pipeline: MEM stage takes one cycle?

Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle: 1 cycle to read a register 4 cycles to reach to L1 cache 10 ...
Wad's user avatar
  • 153
1 vote
1 answer
310 views

Why does this branch data hazard happen during the instruction decode stage?

Suppose I have the following MIPS code on a CPU with forwarding enabled: ...
Zaya's user avatar
  • 175
1 vote
1 answer
2k views

Data hazard after in load word after addi

5 stage pipline addi $t1,$zero,0x30 lw $t2,0($t1) sw $t2,0xff18($zero) addi $t2,$zero,100 Question is to find hazards existing in the code and the answer is:...
nihulus's user avatar
  • 115
1 vote
1 answer
685 views

In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?

In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says Instruction fetch: The top portion of Figure 4.36 shows the instruction being read from ...
Sean Francis N. Ballais's user avatar
1 vote
1 answer
2k views

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
Rajat's user avatar
  • 81
1 vote
1 answer
416 views

How can this MIPS processor execute one instruction in one cycle?

I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris. At the end of the section the autor shows this MIPS processor and ...
EmTor's user avatar
  • 13
1 vote
2 answers
2k views

Represent unsigned 12-bit octal numbers. Results in octal

I have an HW question where I found an answer that matches mine, but their breakdown confuses me. Ques: What is 4365 - 3412 when these values represent unsigned 12-bit octal numbers? The result should ...
David's user avatar
  • 11
1 vote
1 answer
2k views

In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
Khalid Khalil's user avatar
1 vote
2 answers
2k views

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
Ofek .T.'s user avatar
  • 111
1 vote
1 answer
106 views

Byte/word addressing

I am confused on byte addressable/word addressable architecture. I have studied MIPS implementation and I came to know that when the data is retrieved from main memory, it is shifted accordingly to ...
Rajat's user avatar
  • 81
1 vote
1 answer
5k views

How do I calculate Instruction Per Clock?

Hi! I faced a problem with calculating IPC. I can tell the answers were derived from IPC=instruction/number of cycles. But I have no idea why it has to be calculated that way. Just to understand ...
kyung sub Song's user avatar
1 vote
1 answer
48 views

Execution of instruction in MIPS on various parts of the clock cycle

I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...
ronak jain's user avatar
1 vote
1 answer
57 views

Why does it have that amount of stalls

I'm doing an exercise about the MIPS pipeline with the following characteristics: -Branches and Branch targets are calculated in the E-stage. -There is forward logic from the output to the input of ...
begin's user avatar
  • 11
1 vote
0 answers
136 views

Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register

I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
Hoang Nam's user avatar
  • 111
1 vote
0 answers
34 views

Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
Ben's user avatar
  • 11
1 vote
1 answer
1k views

How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw $a0,...
kanayt's user avatar
  • 153
1 vote
0 answers
811 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
HaiLe's user avatar
  • 11
0 votes
2 answers
3k views

how pseudo direct addressing works?

In pseudo direct addressing mode (For the MIPS architecture) the 26 bit of the jump instruction are joined to the upper 4 bits of the PC . how could this help in jumping to relative positions suppose ...
Mahmoud Salah's user avatar
0 votes
1 answer
84 views

R2000 ALU Design

probably a couple decades too late to ask this question, but does anyone know anything/have detailed documentation about the hardware/design underlying the ALU unit in the early MIPS R2000 CPU? ...
shea's user avatar
  • 3
0 votes
1 answer
53 views

How do you tell whether a binary number is positive or negative?

Consider the figure in Exercise 2. If the current machine code that executes is 0x214bfffd and the values of the registers in the processor are as shown below, what is then the value of the input WD3 ?...
First_1st's user avatar
0 votes
2 answers
6k views

lw and sw hazards example MIPS

The below example confused me: lw $r0, 4($r0) sw $r0, 4($r0) add $r0, $r0, $r0 Using MIPS 5 stage execution what are the hazards we have 1) without forwarding 2) ...
alexbako's user avatar
0 votes
1 answer
46 views

What is the hit rate of the cache when executing this code?

C++ code: int main() { short int arr[4][4]; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { arr[i][j] = i+j; } } return 0; } Is there ...
Luke's user avatar
  • 1
0 votes
1 answer
228 views

Why are lw and sw byte addressable but jump and beq word addressable?

I am refering to MIPS (32 bits). Is there any particular reason that when loading or storing a word, we address memory in bytes, but when we jump or branch using beq we address memory in words? Thanks!...
pgiouroukis's user avatar
0 votes
1 answer
2k views

Does higher cpi give better performance?

Does higher cpi give better performance? Lets say there is a code and we can run it by 3 methods. 1 cpi for single cycle 99 cpi for multi cycle 70 cpi for pipeline Multi cycle has the highest cpi for ...
뿌잉뿌줘's user avatar
0 votes
1 answer
752 views

Bytes addressable processor

In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
Rajat's user avatar
  • 81
0 votes
1 answer
295 views

predication, branch prediction question

I have a question about predication and branch prediction. I've emailed my professor regarding this and he replied me that predication has a less instructions than branch prediction. So I tried ...
kyung sub Song's user avatar
0 votes
1 answer
7k views

MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion

I have question about the ALUOp control signal. When doing R type instructions, 31-26th bits are all 000000. What decides the instruction is actually the func field of 5-0th bits. In that case, I ...
kyung sub Song's user avatar
0 votes
1 answer
583 views

MIPS control signal table(R-type add)

I've been going through the control signal table and I noticed something confusing on when I should set the value as 'don't care' or 0 for control signal. For example when doing the R type add ...
kyung sub Song's user avatar
0 votes
1 answer
159 views

Computer Organization and Assembly Language Programming

Why do we need to learn MIPS Assembly language before learning computer organization? What are the implications of learning it first? As a computer scientist, why do we need to learn this one and ...
MonkeyD's user avatar
  • 11
0 votes
0 answers
19 views

Why can't I use data forwarding in this exercise?

as the title says, I am wondering why this exercise doesn't show a data forwarding from the "ex" stage of 2nd instruction to "ex" stage of 3rd instruction. P.S. the architecture is ...
unrealyozora's user avatar
0 votes
0 answers
84 views

How do you determine the amount of bits for the tag, index, and offset in a MIPS byte-addressed direct-mapped cache when given only a list of address?

The question I'm working on is as follows: I'm still kind of working on how direct-mapped caches work in my computer organization class. I sort of understand that you need the least significant 2 ...
mrak-p's user avatar
  • 11
0 votes
1 answer
789 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
Anshul Gupta's user avatar
0 votes
0 answers
155 views

Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
noscreen's user avatar
0 votes
0 answers
213 views

ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
John adams's user avatar
0 votes
1 answer
454 views

Need help converting machine code

I would appreciate some help with this question. The 32 bit numbers below represent a MIPS instruction. identify the different fields and state which instruction it is. give the assembler source code ...
jessie's user avatar
  • 3
0 votes
0 answers
660 views

Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...
user avatar
-1 votes
1 answer
51 views

Computer Architecture MIPS assembler with predictors

This MIPS code is given: ...
Pol's user avatar
  • 11