# Questions tagged [mips]

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### Does higher cpi give better performance?

Does higher cpi give better performance? Lets say there is a code and we can run it by 3 methods. 1 cpi for single cycle 99 cpi for multi cycle 70 cpi for pipeline Multi cycle has the highest cpi for ...
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### Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
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### How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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### Represent unsigned 12-bit octal numbers. Results in octal

I have an HW question where I found an answer that matches mine, but their breakdown confuses me. Ques: What is 4365 - 3412 when these values represent unsigned 12-bit octal numbers? The result should ...
18 views

1k views

### In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
923 views

### Data hazard after in load word after addi

5 stage pipline addi $t1,$zero,0x30 lw $t2,0($t1) sw $t2,0xff18($zero) addi $t2,$zero,100 Question is to find hazards existing in the code and the answer is:...
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### Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
398 views

### In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?

In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says Instruction fetch: The top portion of Figure 4.36 shows the instruction being read from ...
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### Need help converting machine code

I would appreciate some help with this question. The 32 bit numbers below represent a MIPS instruction. identify the different fields and state which instruction it is. give the assembler source code ...
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I am confused on byte addressable/word addressable architecture. I have studied MIPS implementation and I came to know that when the data is retrieved from main memory, it is shifted accordingly to ...
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### How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw \$a0,...
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### CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
2k views

### Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
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### predication, branch prediction question

I have a question about predication and branch prediction. I've emailed my professor regarding this and he replied me that predication has a less instructions than branch prediction. So I tried ...
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### Predication execution

I was studying branch prediction & predication execution and faced a trouble.. I'm not quite sure whether I understood the concept of predication but based on what I have learned it is taking ...
3k views

### How do I calculate Instruction Per Clock?

Hi! I faced a problem with calculating IPC. I can tell the answers were derived from IPC=instruction/number of cycles. But I have no idea why it has to be calculated that way. Just to understand ...
3k views

### MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion

I have question about the ALUOp control signal. When doing R type instructions, 31-26th bits are all 000000. What decides the instruction is actually the func field of 5-0th bits. In that case, I ...
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### MIPS control signal table(R-type add)

I've been going through the control signal table and I noticed something confusing on when I should set the value as 'don't care' or 0 for control signal. For example when doing the R type add ...
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### MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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### Computer Organization and Assembly Language Programming

Why do we need to learn MIPS Assembly language before learning computer organization? What are the implications of learning it first? As a computer scientist, why do we need to learn this one and ...