Questions tagged [mips]

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11
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3answers
2k views

Are there competitions for integer programming?

Are there competitions for integer programming like there are for SAT and MAXSAT?
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0answers
10 views

Is there a tool or simulator for 5 stage mips pipeline that detects data and control hazards? [closed]

Title says it all. Tried different tools but was not successful.
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0answers
11 views

Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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0answers
15 views

why we need pipeline registers in pipeline processor ( as for example for MIPS processor )

I think the answer because the data of an instruction can be overridden by the data of the instruction that will be fetched after it , but I think the data of the first instruction will always be ...
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0answers
24 views

If there is a cache miss can we consider extra memory accesses because it has to fetch data from the main memory?

A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store ...
0
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1answer
62 views

Why is the opcode 0 for all r-type instructions? Please explain your answer

I can't seem to find the explanation for why all r-type instructions have opcode 0 always. Can anybody explain why this is so.
0
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2answers
306 views

how pseudo direct addressing works?

In pseudo direct addressing mode (For the MIPS architecture) the 26 bit of the jump instruction are joined to the upper 4 bits of the PC . how could this help in jumping to relative positions suppose ...
0
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0answers
42 views

Linker question in MIPS

The above is the example from section 2.12 Translating and Starting a Program from Computer Organization and Design, Fifth Edition, The Hardware/Software Interface, by David A. Patterson and John L. ...
1
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1answer
619 views

In instructions pipelining, why does register read/write take up only half clock cycle?

While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
1
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1answer
543 views

Data hazard after in load word after addi

5 stage pipline addi $t1,$zero,0x30 lw $t2,0($t1) sw $t2,0xff18($zero) addi $t2,$zero,100 Question is to find hazards existing in the code and the answer is:...
1
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0answers
23 views

Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
0
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1answer
202 views

Bytes addressable processor

In MIPS processor, address bus is of 32 bits. So on addressing an instruction, a whole 32 bit instruction is fetched. How is it byte addressable then? I mean if on addressing a particular address, the ...
1
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1answer
246 views

In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?

In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says Instruction fetch: The top portion of Figure 4.36 shows the instruction being read from ...
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2answers
488 views

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
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1answer
48 views

Need help converting machine code

I would appreciate some help with this question. The 32 bit numbers below represent a MIPS instruction. identify the different fields and state which instruction it is. give the assembler source code ...
3
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1answer
98 views

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to ...
1
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1answer
621 views

How to reach data segment from global pointer in MIPS?

The global pointer is initialized to 01x10008000. The data segment starts at 0x1000000. I want to load the first word found in the data segment. So I place 0x8000 in the address field of lw. lw $a0,...
1
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1answer
60 views

Byte/word addressing

I am confused on byte addressable/word addressable architecture. I have studied MIPS implementation and I came to know that when the data is retrieved from main memory, it is shifted accordingly to ...
0
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1answer
1k views

Bubble in a pipeline

When NOPs are introduced in the pipeline by the control unit, how does they really cause the pipeline to stall? I mean, at every clock cycle, the pipeline register will eventually forward its contents ...
0
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1answer
132 views

predication, branch prediction question

I have a question about predication and branch prediction. I've emailed my professor regarding this and he replied me that predication has a less instructions than branch prediction. So I tried ...
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3answers
320 views

Predication execution

I was studying branch prediction & predication execution and faced a trouble.. I'm not quite sure whether I understood the concept of predication but based on what I have learned it is taking ...
1
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1answer
2k views

How do I calculate Instruction Per Clock?

Hi! I faced a problem with calculating IPC. I can tell the answers were derived from IPC=instruction/number of cycles. But I have no idea why it has to be calculated that way. Just to understand ...
0
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1answer
2k views

MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion

I have question about the ALUOp control signal. When doing R type instructions, 31-26th bits are all 000000. What decides the instruction is actually the func field of 5-0th bits. In that case, I ...
0
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1answer
353 views

MIPS control signal table(R-type add)

I've been going through the control signal table and I noticed something confusing on when I should set the value as 'don't care' or 0 for control signal. For example when doing the R type add ...
1
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0answers
468 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
0
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1answer
123 views

Computer Organization and Assembly Language Programming

Why do we need to learn MIPS Assembly language before learning computer organization? What are the implications of learning it first? As a computer scientist, why do we need to learn this one and ...
2
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0answers
166 views

Why do processor designers allow some pipeline hazards to occure [closed]

Actually this is a exam paper question I found during studying pipelined MIPS architecture.My idea is designers allow to occur hazards because of the cost to make complex design to prevent hazards,so ...
0
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2answers
3k views

lw and sw hazards example MIPS

The below example confused me: lw $r0, 4($r0) sw $r0, 4($r0) add $r0, $r0, $r0 Using MIPS 5 stage execution what are the hazards we have 1) without forwarding 2) ...
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0answers
640 views

Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...