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Questions tagged [mips]

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Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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1answer
38 views

Represent unsigned 12-bit octal numbers. Results in octal

I have an HW question where I found an answer that matches mine, but their breakdown confuses me. Ques: What is 4365 - 3412 when these values represent unsigned 12-bit octal numbers? The result should ...
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0answers
78 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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28 views

Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
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0answers
570 views

MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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22 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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17 views

MIPS pipelining stage used for commands

lw $4, 40($4) sw $4, 50($4) add $4, $4, $4 Suppose the above code was to be executed using 5 stage pipelining. I want to determine the data hazards but I am ...
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26 views

Identifying problem in MIPS pipeline datapath

I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
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9 views

Data Hazards and stalls

I am studying for my exam tomorrow and I am having difficulty in the below code : sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Due ...
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43 views

ALU-Store data hazard

Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding : ...
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2answers
759 views

Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
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642 views

Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...