Questions tagged [mips]

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Detecting Data and Control Hazards for a mips 5 stage pipeline

I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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Given a set of solutions, find an IP formulation with the same solution set

Input: A list of integer variables $x_1, ..., x_n$. A finite set of feasible solutions $S \subset \mathbb{Z}^n$. Task: Find an integer linear program (IP) on the integer variables $x_1,...,x_n$ ...
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MIPS Pipeline Hazards - Branch Delay Slot

I'm confused about this exercise. We have assembly code: ...
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why we need pipeline registers in pipeline processor ( as for example for MIPS processor )

I think the answer because the data of an instruction can be overridden by the data of the instruction that will be fetched after it , but I think the data of the first instruction will always be ...
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If there is a cache miss can we consider extra memory accesses because it has to fetch data from the main memory?

A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store ...
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Linker question in MIPS

The above is the example from section 2.12 Translating and Starting a Program from Computer Organization and Design, Fifth Edition, The Hardware/Software Interface, by David A. Patterson and John L. ...
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Data hazard or forward in MIPS SW after LW in this case?

so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes. Look at this piece of code: ...
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Branch delay slots in MIPS architecture

I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory ...