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Questions tagged [shared-memory]

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3 votes
1 answer

Help understanding Petersons Algorithm for N Processes

I read the wikipedia article: What I don't understand is how the algorithm is guaranteed to work when the processor or processors are switching ...
FourierFlux's user avatar
5 votes
1 answer

Understanding IBM370 Relaxed Memory Consistency

In the report "Shared Memory Consistency Models: A Tutorial" (, the authors explain the difference between IBM370, Total Store ...
KevS's user avatar
  • 51
2 votes
1 answer

Why sequential consistency model is widely used if it is unsound

From this talk and these lecture notes here and here I learned that sequential consistency does not actually model what really happens in practice. However, it is also pointed out that most of the ...
Barte's user avatar
  • 503
0 votes
1 answer

Method of communication in Distributed Systems

Why the method of communication used in DS is message passing and not shared memory ?
John adams's user avatar
0 votes
1 answer

Usefulness of consensus number

What information and usefulness does knowing the consensus number of a shared object give me?
Bruce Wayne's user avatar
1 vote
0 answers

'if' and 'while' statements within a SIMD architecture and its memory architecture

I am doing some past exam papers and I found two interesting questions which I cannot answer due to them not being extensively covered in the lecture notes given to me by my lecturer. The questions ...
Green Manalishi 's user avatar
1 vote
1 answer

Conway's Game Of Life Problem Parallel (OpenMP)

I am currently working in solving Conway's Game Of Life problem for a Parallel and Distributed Computing course. The problem is a little bit different form the original, in the sense that instead of ...
jbernardo's user avatar
2 votes
0 answers

Processor consistency and cache coherence

Consider this example from Wikipedia: ...
tierriminator's user avatar
2 votes
0 answers

Write-To-Read Relaxation in Cache Consistency

Write-to-Read Relaxation means that for a processor: later reads can bypass earlier writes But what does that mean? What exactly is the difference between a read and a write for a Cache? An ...
Seen's user avatar
  • 83
3 votes
0 answers

Wikipedia on MVCC

I read about Multiversion Concurrency Control in Wikipedia. They say that every piece of data in DB has a Read Time Stamp (RTS) and If transaction Ti wants to Write to object P, and there is also ...
Little Alien's user avatar
1 vote
1 answer

Effect of Copy-On-Write on 2 processes sharing address space

I am studying operating systems and was going through Copy On Write mechanism. From Wiki: When one process modifies the memory, the operating system's kernel intercepts the operation and copies ...
Mojo Jojo's user avatar
  • 173
9 votes
1 answer

Why is quiescent consistency compositional, but sequential consistency is not

I'm having trouble in comparing these two memory consistency models. Essentially for sequential consistency I think of real code like this: ...
William's user avatar
  • 193
4 votes
1 answer

Difference between SRSW and MRSW safe Boolean registers

I'm reading The Art of Multiprocessor Programming and am currently trying to understand Chapter 4 — The Foundations of Shared Memory. In section 4.2 it is shown how to build a multi-reader, single-...
Ionuț G. Stan's user avatar
2 votes
2 answers

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
ghostloops's user avatar
4 votes
0 answers

Extending the causal memory model to wide-area distributed storage systems

In the seminal paper "Causal memory: definitions, implementations, and programming", distributed causal memory is defined to ensures that all the processes in a system agree on the relative ordering ...
hengxin's user avatar
  • 9,561
22 votes
1 answer

Memory Consistency vs Cache Coherence

Is it true that Sequential Consistency is a stronger property than Cache Coherence? According to Sorin, Daniel J; Hill, Mark D; Wood, David A: A Primer on Memory Consistency and Cache Coherence, ...
Ayrat's user avatar
  • 1,075
6 votes
1 answer

Why can L3 caches hold only shared blocks?

In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches (e....
Raphael's user avatar
  • 72.5k
5 votes
1 answer

termination of two concurrent threads with shared variables

We're in a shared memory concurrency model where all reads and writes to integer variables are atomic. do: $S_1$ ...
Gilles 'SO- stop being evil''s user avatar