Questions tagged [shift-register]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
0 votes
0 answers

DJNZ command in Universal Register Machine

How do I represent DJNZ command of counting machine via commands of Universal Register Machine, those commands are CLR JNE INC and TR, via this commands i have to represent DJNZ command, any help ...
Tarik 's user avatar
1 vote
1 answer

Generate degree-bound LFSR to approximate given sequence

Given an output sequence, $S$, we can use the Berlekamp-Massey algorithm to find the shortest LFSR, of order $n \leq |S|$, which exactly generates that sequence. Is it possible to efficiently compute ...
Alex P's user avatar
  • 148
1 vote
0 answers

How to cascade register correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
sttc1888's user avatar
1 vote
0 answers

How can I get 8 bits output from 4 bit CPU?

I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
sttc1888's user avatar
0 votes
0 answers

Asking for your help with LFSR, linear automaton

I am a software developer new to the site. I am currently learning about LFSR (linear feedback shift register). Every day I solve a question which is given to me, but today I am lost. I can not solve ...
endoftheworld's user avatar
1 vote
1 answer

What is the purpose of a single input, single output, bidirectional shift register?

(source: This is the sort of bidirectional shift register, I'm talking about. I understand why the normal right shift is useful, but when you shift it left, all you're really doing is sending ...
Physco111's user avatar
  • 111
1 vote
1 answer

For what $N$ does $2^N$ overflow?

Consider the following computation: 2^N (TWO TO THE POWER OF ‘N’, for Int. N>0), being executed on a processor with 32 bit internal, user and ALU registers. The registers rightmost bit is bit 0 and ...
Nick Powers's user avatar
0 votes
1 answer

Register Transfer Activity

In a simple architecture(not considering parallel architecture) how exactly this can be performed in a single clock cycle: P:R1 <- R2, R2 <-R1 where R1 and R2 are registers and P is a control ...
saladi's user avatar
  • 119
4 votes
1 answer

LFSR sequence computation

I need to calculate the output of the sequence generated by this shift register but I cannot find anywhere how to do it. Everywhere the results are just given but there is no explanation how to do ...
user1047517's user avatar
13 votes
1 answer

Choosing taps for Linear Feedback Shift Register

I am confused about how taps are chosen for Linear Feedback Shift Registers. I have a diagram which shows a LFSR with connection polynomial $C(X) = X^5 + X^2 + 1$. The five stages are labelled: $R4, ...
sam's user avatar
  • 357