Questions tagged [virtual-memory]

Questions about techniques for providing the appearance of an isolated, contiguous address space to each process. The size of the address spaces may be made to appear larger than the size of main memory by moving pages or segments between main memory and a larger backing store.

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can virtual address map any on virtual memory on disk?

I was reading a textbook which says that: If the valid bit is set, the address field indicates the start of the corresponding physical page in DRAM where the virtual page is cached. If the valid bit ...
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How does virtual memory work when it need to save data in physical memory into disk?

I'm reading a textbook which desribe VM as: a data structure stored in physical memory known as a page table that maps virtual pages to physical pages. The address translation hardware reads the page ...
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Question regarding the one and two level paging system

I am studying for my OS final exam and I am solving some problems related to virtual memory . however , I have faced a problem which I need to test my understanding regarding it : ...
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How does the OS handle multiple stacks in its physical memory?

Without assuming ASLR... Processes have virtual addresses, and they manage stacks & heaps of their own. However, these all get mapped to physical addresses somewhere on the memory. Let's say we ...
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43 views

Virtual Memory vs Cache for block identification

Both are based on the principle of locality. Then why virtual memory uses table lookup while cache memory uses associative memory for block identification?
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Source code or detailed explanation of “WKS” virtual memory compression algorithm?

I've been trying to find information on various program data virtual memory compression algorithms that are in the "WK" family of algorithms. So far, I've been successful with the "WKdm" compression ...
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33 views

Hierarchical page tables with page size of 8 KB

Consider a machine with a physical memory of 8 GB, a page size of 8 KB, and a page table entry size of 4 bytes. How many levels of page tables would be required to map a 46-bit virtual address space ...
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35 views

Is physical pages zeroed out before it's mapped to a virtual page?

I don't how this works. According to me if the physical memory is not cleared then there is some security risk as there may be some sensitive information in it from the other processes. How does the ...
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2answers
45 views

Determine page number and offsets for address references

I'm working on learning operating systems and I've come across a strange question that I don't know how to answer. The question is: Assuming a 1-KB page size, what are the page numbers and offsets ...
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What does this mean: “The compile-time and load-time address-binding methods generate identical logical and physical addresses”?

I read this in my Operating System textbook. Does it mean that the logical addresses generated by compile-time binding scheme are the same as the logical addresses generated by load-time binding? Or ...
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Doubt in effective memory access time in case of n level paging + TLB

I am getting confused with calculation of EEMAT(Effective memory access time). I decided to close the book and think on my own and make an equation. Please see whther this is correct or not. I thought ...
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Study of cache behaviour of algorithms on Virtualbox

I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general. I want to understand, is it advisable, if I do this study in an virtualized ...
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1answer
26 views

Paging - access less than a page of memory

I'm having a bit of trouble understanding how less than a page of memory can be used. From what I understand, memory is given out in page size chunks - say pages are 4096 bytes, and 4 bytes are ...
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How does increase in main memory affects cache performance?

I know advantages of increase in main memory like more pages , better Spatial locality of reference , more number of processes in main memory and increase in CPU performance. What can be disadvantages ...
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What happen if the L1 cache has the address entry with write_back attribute. Will that address be available in L2 cache?

I have the TLB entry for a particular address. This address has write-back attributes in both L1 cache and L2 cache. My queries are: 1> if L1 cache entry has write-back, can it be write-back in L2? 2> ...
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64 views

Distinction between paging and segmentation?

In my operating systems textbook, there is a paragraph which states: As for the contents of each PTE, we have a number of different bits in there worth understanding at some level. A valid bit is ...
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384 views

What are the differences between embedded processor and non-embedded processor?

I read a statement which says Almost all non-embedded processors, and many embedded processors, support virtual memory Anyone who can explain the difference between both types
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Understanding memory mapping conceptually

I've already read several blogs and questions on stack exchange, but I'm unable to grasp what the real drawbacks of memory mapped files are. I see the following are frequently listed: You can't ...
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53 views

Software management of TLB misses?

I'm reading an OS textbook and it was talking about TLB misses being handled by software. I'm very new to all this by the way. So there's a context switch to some kernel procedure. But surely in this ...
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52 views

How are logical addresses of instruction operands mapped to physical addresses?

Is address translation for all operands in single instruction done only once and then are all operands fetched continuously? For example, consider any dummy instruction ...
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47 views

Slowdown when accessing data at page boundaries?

Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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1answer
281 views

Understanding paging and internal fragmentation

I am currently studing questions but stuck on this one, I hope someone can help me out to understand. Question: Assume that we have a paged virtual memory with a page size of 4Ki byte. Assume that ...
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2answers
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Do the “virtual memory”s mentioned in the 2 articles refer to different things?

I've read the following 2 articles explaining the difference between virtual memory and physical memory. One thing that I found ...
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1answer
35 views

Virtual address translation

I'm in an OS class now. I've been wrestling this problem for a while and can't convince myself of a solution. My professor is very busy and hasn't made time to help. Also, this question is from an ...
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Machine code: How can an OS prevent user-level programs from accessing each other's memory? [duplicate]

Okay, I’ve done a lot of research on this, but I can’t seem to wrap my head around it. Essentially, the question is as follows: How can an operating system prevent a machine instruction from a user-...
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220 views

Memory Mapping Segment

I read that "Memory Mapping Segment"/"memory mapped file" is a segment of the virtual memory of a process, where a file or file-like Ressource is loaded into. It is for high performance file I/O. I ...
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address spaces of changing processes

I read that the mapping for user-space processes is changed after each process switch. By mapping I mean the translation from virtual addresses to "real" memory address. I thought that processes are ...
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1answer
220 views

What does it mean " The outer level page table need not be page aligned?

The question is in context to multilevel page table. I was trying to solve numerical on multi-level paging and noticed that page size might not be same at all levels. I came across the point "Outer ...
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1answer
70 views

ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
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1answer
51 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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pool of free page frames OS

I read that in a paging scheme memory management, some os's have a paging daemon that wakes up periodically to inspect the memory of the RAM. This is to ensure that modified pages can be scheduled to ...
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402 views

Effective Instruction Execution Time with TLB and page Fault

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds ...
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302 views

How can a user process even try to access a memory location its not allowed to when it doesn't have access to page table?

So is it even possible for a user process to even try to access a physical memory location that does not belong to it and therefore getting an error by operating system? because for example with a 32 ...
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344 views

How pictures and videos are usually loaded in Memory? [closed]

Lets assume I'm talking about Jpeg and Mp4 and a general video player(not sure if different ones load it differently, if they do please tell) So do video players (process) usually load the entire ...
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1answer
221 views

How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: List item before effective address calculation has started during effective ...
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119 views

why do we run out of heap space even if we have virtual memory?

Whenever we try to get space in heap(using malloc or new) we can get out of heap space error if it exceeds the limit. But, we have virtual memory so why can't OS allocate that much space and then do ...
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1answer
38 views

Transform calculation to memory

Theoretically, is it possible to convert the processing power of the CPU into several tens of bits of memory? My question is unusual, but it's very interesting. I'm looking for a way to create a ...
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1answer
311 views

Valid bit incoherence between TLB and Page Table

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
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Linux OS/HW VM cooperation

From what i've learned, the HW is responsible for setting the accessed and dirty bits in the PTE of a process, and the OS is responsible for turning them off. My question is why? The first part, i ...
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72 views

Virutalization of peripheral device

I have this question to answer: "Please shortly explain how an interface virtualizes a peripheral device to the CPU." I don't really understand what the question is asking for. I know the theory ...
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2answers
265 views

Does the Working Set Paging Algorithm use a separate page table?

I am doing research on paging algorithms. While learning about the working set algorithm from several scientific sources I was not really able to figure out where exactly the working set is defined or ...
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59 views

Working out logical address space

If I have 2^32 bytes (512 MB) of physical memory, and we assume that each page is 2^10 bytes, how would I work out what the physical and logical address space would be? No explanation that I can find ...
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872 views

Definitions of: virtual address space, page size

(I can't seem to find actual definitions of these terms anywhere, only hints and guesses). Is it fair to say, that: Virtual address space is the amount of bytes that can fit into RAM cells of all ...
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2answers
72 views

How does the processing happen in a CPU when it uses Virtual Memory?

I am just trying to visualize how computers work with Virtual Memory/Address. Assume there is a program on the disk that looks like this: ...
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1answer
202 views

What's a bank memory?

I've search on Google but still don't understand. I've read about it into arm book, but they don't define it. Could you explain me what is it, where is it used, what's the point to have it and, if ...
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59 views

TLB failure in a memory access

I have come across a question which says If there is a TLB failure in a memory access, the disk must be accessed to load a new page into main memory. The answer is NO, but i dont understand why. Is ...
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110 views

Process address space separation in L1 cache of Intel hyperthreaded CPUs

Since a processing core with hyperthreading enabled is presented as two or more cores to the operating system, it can run completely different processes with different, isolated virtual memory spaces. ...
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2answers
111 views

What is the difference between a page and thread?

"Each process that is executed is divided into blocks of same size, called pages." "Thread is a part of process being executed." Are pages and threads both part(s) of process? Whats the difference ...
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188 views

How does a buffer overrun corrupt the return address?

I got stuck on the following note while reading a paper about computer security: The stack mixes program data and control data – by overrunning buffers on the stack we can corrupt the return ...
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126 views

Virtual Memory: “Page Table or Page Tables?”

I am having a bit of a tough time grasping whether a computer system contains several page tables or just one page table. Some sources speak of page tables in plural others in singular. ...