Questions tagged [virtual-memory]

Questions about techniques for providing the appearance of an isolated, contiguous address space to each process. The size of the address spaces may be made to appear larger than the size of main memory by moving pages or segments between main memory and a larger backing store.

23 questions with no upvoted or accepted answers
Filter by
Sorted by
Tagged with
5
votes
0answers
429 views

When there's no memory, should malloc or read/write fail?

To my surprise, I recently found out that Windows would fail a large memory allocation even if little of said memory is to actually be used, e.g. even if you don't want the swap, you better not ...
4
votes
2answers
504 views

Paging: Does the page table of a process also gets swapped out when the process gets swapped out from main memory?

Does a process's page table too gets swapped out to secondary storage from main memory when the process gets swapped out to secondary storage from main memory? And gets swapped back in when the ...
3
votes
0answers
125 views

Isn't resident set management superfluous?

My question is in the context of a paging virtual memory system. THE PREMISES: The function of resident set management (RSM) is to: Impose an upper bound on the cardinality of a process' resident ...
2
votes
0answers
751 views

How are LRU and Clock algorithm different?

I am modeling the Gclock-pro buffer replacement algorithm in Linux kernel. Because there are many existing modeling works on LRU, I am considering adopting LRU model to roughly describe Gclock-pro, ...
2
votes
1answer
2k views

Maximum amount of memory that can be allocated to a process

DISCLAIMER: The following scenario was taken from an assignment I got in a OS course I'm taking, and it arose a lot of question marks in my head. However non of the questions asked by myself here ...
1
vote
2answers
34 views

How are programs split up into pages in Memory Paging?

I am a bit confused about how the logical addresses are generated in a paging memory architecture and where and when a program is split up into pages. I understand how logical addresses are translated ...
1
vote
2answers
114 views

Determine page number and offsets for address references

I'm working on learning operating systems and I've come across a strange question that I don't know how to answer. The question is: Assuming a 1-KB page size, what are the page numbers and offsets ...
1
vote
0answers
329 views

pool of free page frames OS

I read that in a paging scheme memory management, some os's have a paging daemon that wakes up periodically to inspect the memory of the RAM. This is to ensure that modified pages can be scheduled to ...
1
vote
1answer
2k views

Does Second chance Page replacement algorithm suffer with Belady's anomaly?

In Second chance Page replacement algorithm(clock algorithm), if all the Reference bits are set to one, then the algorithm behaves just as FIFO. Considering this case, can we conclude that Second ...
0
votes
0answers
20 views

Is logical to physical address conversion inclusive?

If I am trying to translate a logical address of page N and offset O, and my translation unit tells me the translation has a base address of B and a length of L, is the length L inclusive or will it ...
0
votes
0answers
12 views

Functionning of the eviction set for Prime and Probe

I have to write a report about Prime and Probe, more specifically about its eviction set method, and there are two notions that remain blurry for me : To find the set, we use huge pages like it's ...
0
votes
0answers
24 views

Question regarding the one and two level paging system

I am studying for my OS final exam and I am solving some problems related to virtual memory . however , I have faced a problem which I need to test my understanding regarding it : ...
0
votes
0answers
29 views

Source code or detailed explanation of “WKS” virtual memory compression algorithm?

I've been trying to find information on various program data virtual memory compression algorithms that are in the "WK" family of algorithms. So far, I've been successful with the "WKdm" compression ...
0
votes
0answers
42 views

Hierarchical page tables with page size of 8 KB

Consider a machine with a physical memory of 8 GB, a page size of 8 KB, and a page table entry size of 4 bytes. How many levels of page tables would be required to map a 46-bit virtual address space ...
0
votes
0answers
44 views

Doubt in effective memory access time in case of n level paging + TLB

I am getting confused with calculation of EEMAT(Effective memory access time). I decided to close the book and think on my own and make an equation. Please see whther this is correct or not. I thought ...
0
votes
0answers
445 views

Effective Instruction Execution Time with TLB and page Fault

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds ...
0
votes
0answers
61 views

Working out logical address space

If I have 2^32 bytes (512 MB) of physical memory, and we assume that each page is 2^10 bytes, how would I work out what the physical and logical address space would be? No explanation that I can find ...
0
votes
0answers
59 views

TLB failure in a memory access

I have come across a question which says If there is a TLB failure in a memory access, the disk must be accessed to load a new page into main memory. The answer is NO, but i dont understand why. Is ...
0
votes
0answers
69 views

What happens when accessing 0x00ABBA?

Given the following page table with a 24 Bit virtual address and 4KB page size and 4 byte long entries (%X means hexadecimal values): I don't understand how to translate e.g. address %X00ABBA here. I ...
0
votes
0answers
51 views

Can the cache always miss while trying to write to the cache?

According to the lecture, a virtual address first goes to the TLB. If the TLB hits, it is then checked, if something has to be either read or written from cache. In case of writing, it is then ...
0
votes
0answers
467 views

Roles of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
0
votes
0answers
226 views

What are current cache algorithms and cache strategies?

Which cache strategies/algorithms (especially for L2 Cache) are used in practice and don't exist solely in research/theory? There is a list on Wikipedia which does not state which algorithms are ...
-1
votes
1answer
609 views

What are the differences between embedded processor and non-embedded processor?

I read a statement which says Almost all non-embedded processors, and many embedded processors, support virtual memory Anyone who can explain the difference between both types