Questions tagged [virtual-memory]

Questions about techniques for providing the appearance of an isolated, contiguous address space to each process. The size of the address spaces may be made to appear larger than the size of main memory by moving pages or segments between main memory and a larger backing store.

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Question on Virtual memory and Physical memory

This is the question where I'm stuck: With a 32-bit virtual address, 4 KB pages(12 offset bits), and 4 bytes per page table entry, we can compute the total page table size: Number of page table ...
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363 views

In an Inverted Page Table, will following chains happen very often for small addresses?

I just learned about the Inverted Page Table and immediately thought about the chaining model used. If two processes use the same virtual address, resolving the address will have to include following ...
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1k views

Does virtual address space resides in virtual memory?

I have several confusion like : Does virtual address space resides in virtual memory ? Does each process has its own virtual address space like each process has its own virtual memory and own page ...
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289 views

clarification about Algorithm of page replacement LRU with reference bits

Studying LRU approximation Algorithms I think to have not understand how it works, for example: ...
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1answer
16 views

Paging - access less than a page of memory

I'm having a bit of trouble understanding how less than a page of memory can be used. From what I understand, memory is given out in page size chunks - say pages are 4096 bytes, and 4 bytes are ...
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1answer
44 views

How are logical addresses of instruction operands mapped to physical addresses?

Is address translation for all operands in single instruction done only once and then are all operands fetched continuously? For example, consider any dummy instruction ...
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639 views

Definitions of: virtual address space, page size

(I can't seem to find actual definitions of these terms anywhere, only hints and guesses). Is it fair to say, that: Virtual address space is the amount of bytes that can fit into RAM cells of all ...
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1answer
9k views

Explain Hashed page tables in operating system

I have a difficult time understanding hashed page tables used in virtual memory management. Here is picture of the slide that I am referring to: I understand that p is hashed and then the hash is ...
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1answer
48 views

Is the term page replacement actually a misnomer?

My understanding is that "page replacement" entails replacing the contents of a frame to bring in a new frame in it's place corresponding to a new page. Since it is not the page, but the frame that ...
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334 views

Address space definition

I'm learning by my self about OS theory and I have some troubles to understand what is a process address space. So far, I came across two definitions of what a process address space is: 1 - The set ...
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pool of free page frames OS

I read that in a paging scheme memory management, some os's have a paging daemon that wakes up periodically to inspect the memory of the RAM. This is to ensure that modified pages can be scheduled to ...
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1answer
80 views

Process address space separation in L1 cache of Intel hyperthreaded CPUs

Since a processing core with hyperthreading enabled is presented as two or more cores to the operating system, it can run completely different processes with different, isolated virtual memory spaces. ...
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1answer
2k views

Does Second chance Page replacement algorithm suffer with Belady's anomaly?

In Second chance Page replacement algorithm(clock algorithm), if all the Reference bits are set to one, then the algorithm behaves just as FIFO. Considering this case, can we conclude that Second ...
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1answer
215 views

Valid bit incoherence between TLB and Page Table

In the fourth row of the TLB the valid bit is 0. The corresponding row in the pagle table (fifht row) has the valid bit 1. How is this possible? What events leads to this incoherence?
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Does MMU contain and manage CPU caches?

I read about Virtual Memory in various CS references, however I'm still not sure whether CPU caches such as TLB, L1 and L2 are ...
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24 views

Do the “virtual memory”s mentioned in the 2 articles refer to different things?

I've read the following 2 articles explaining the difference between virtual memory and physical memory. One thing that I found ...
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1answer
479 views

Why is the processes address space a continuous block in RAM?

I need some clarification regarding how the process address space is organized in memory. I went through basic concepts of virtual memory and adress translation and according to the size of the page, ...
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1answer
451 views

How does cpu fetch active program data (using virtual address) from storage when there is a page fault?

I read that cpu generates virtual address and using the same mmu translates to physical address and then fetches the data from RAM. But when there is a page fault, the data is fetched from the HDD(or ...
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1answer
37 views

Distinction between paging and segmentation?

In my operating systems textbook, there is a paragraph which states: As for the contents of each PTE, we have a number of different bits in there worth understanding at some level. A valid bit is ...
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120 views

Virtual Memory: “Page Table or Page Tables?”

I am having a bit of a tough time grasping whether a computer system contains several page tables or just one page table. Some sources speak of page tables in plural others in singular. ...
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5answers
257 views

Is Virtual Memory unreliable?

I have a question regarding multilevel page tables. As far as I know, in most 64 bit systems only 48 bits are used in page tables which would allow for 256TB of virtual memory to be addressed. For ...
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1answer
1k views

What is the overhead of Virtual Memory?

What is the price paid for the vast virtual address space provided to programmers for their applications? Or in other words, what is the overhead due to virtual memory? Is there any other overhead ...
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72 views

In memory paging, how does the S.O. know where the page is in secondary Memory?

So every process has its own Page Table, the page table references the frame where the page is in physical memory and also has a valid-invalid bit that tells whether it is in physical memory or in ...
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1answer
1k views

Segmentation and paging

I am given a system with a segmented paging architecture. Both physical and virtual address spaces contain $2^{16}$ bytes each. The virtual address space is divided in $8$ equal size segments. The ...
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78 views

Understanding memory mapping conceptually

I've already read several blogs and questions on stack exchange, but I'm unable to grasp what the real drawbacks of memory mapped files are. I see the following are frequently listed: You can't ...
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1answer
49 views

Software management of TLB misses?

I'm reading an OS textbook and it was talking about TLB misses being handled by software. I'm very new to all this by the way. So there's a context switch to some kernel procedure. But surely in this ...
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1answer
130 views

Understanding paging and internal fragmentation

I am currently studing questions but stuck on this one, I hope someone can help me out to understand. Question: Assume that we have a paged virtual memory with a page size of 4Ki byte. Assume that ...
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1answer
32 views

Virtual address translation

I'm in an OS class now. I've been wrestling this problem for a while and can't convince myself of a solution. My professor is very busy and hasn't made time to help. Also, this question is from an ...
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1answer
62 views

Memory Mapping Segment

I read that "Memory Mapping Segment"/"memory mapped file" is a segment of the virtual memory of a process, where a file or file-like Ressource is loaded into. It is for high performance file I/O. I ...
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1answer
60 views

ARM STM instruction: page fault problem with MMIO

The ARM STM instruction is described here in the ARM manual. This instruction writes all or a subset of registers at memory locations starting from a base memory ...
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1answer
41 views

jump to MMIO address

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)? Would this ...
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1answer
163 views

How can a user process even try to access a memory location its not allowed to when it doesn't have access to page table?

So is it even possible for a user process to even try to access a physical memory location that does not belong to it and therefore getting an error by operating system? because for example with a 32 ...
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1answer
36 views

Linux OS/HW VM cooperation

From what i've learned, the HW is responsible for setting the accessed and dirty bits in the PTE of a process, and the OS is responsible for turning them off. My question is why? The first part, i ...
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1answer
59 views

Virutalization of peripheral device

I have this question to answer: "Please shortly explain how an interface virtualizes a peripheral device to the CPU." I don't really understand what the question is asking for. I know the theory ...
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2answers
70 views

How does the processing happen in a CPU when it uses Virtual Memory?

I am just trying to visualize how computers work with Virtual Memory/Address. Assume there is a program on the disk that looks like this: ...
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1answer
132 views

What's a bank memory?

I've search on Google but still don't understand. I've read about it into arm book, but they don't define it. Could you explain me what is it, where is it used, what's the point to have it and, if ...
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1answer
130 views

How does a buffer overrun corrupt the return address?

I got stuck on the following note while reading a paper about computer security: The stack mixes program data and control data – by overrunning buffers on the stack we can corrupt the return ...
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1answer
99 views

RAM and the degrees of freedom

This question is about computation/computational physics. Imagine that you want to solve $10^6$ equations of motion, and you have $10^6$ degrees of freedom (position of the particle). How many RAM ...
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1answer
7k views

How many bits for offset/frame/page

I'm working on the following exercise and can't get the calculations right: Assume an OS uses: 33 bits for physical address 34 bits for logical address 2KB frame size Calculate: How many bits are ...
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1answer
3k views

Page vs page table entry

Im studying for OS-finals and I cant figure out the difference. A page is a chunk of addresses e.g 0-4095. This maps to 4kB of memory. This page is 4kB big. But according to the litterature the Page ...
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1answer
2k views

finding maximum virtual and physical memory

If the following is given: CPU uses a four-level hierarchical page table, each level can contain 512 entries the page size is 4KB. virtual address is 48 bits How do i get the size of the virtual ...
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3answers
720 views

Operating System Paging concept

I am quoting a paragraph from the book "Operating System Principles" by Galvin. Usually, each page-table entry is 4 bytes long, but that size can vary as well. A 32-bit entry can point to one of $2^...
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1answer
53 views

Name for almost random memory distribution on the heap

If I had a heap like the following: with blue blocks being occupied memory and white blocks being free memory What is the general name given to the situation illustrated, where the free and occupied ...
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16 views

Doubt in effective memory access time in case of n level paging + TLB

I am getting confused with calculation of EEMAT(Effective memory access time). I decided to close the book and think on my own and make an equation. Please see whther this is correct or not. I thought ...
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8 views

Study of cache behaviour of algorithms on Virtualbox

I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general. I want to understand, is it advisable, if I do this study in an virtualized ...
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16 views

How does increase in main memory affects cache performance?

I know advantages of increase in main memory like more pages , better Spatial locality of reference , more number of processes in main memory and increase in CPU performance. What can be disadvantages ...
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What happen if the L1 cache has the address entry with write_back attribute. Will that address be available in L2 cache?

I have the TLB entry for a particular address. This address has write-back attributes in both L1 cache and L2 cache. My queries are: 1> if L1 cache entry has write-back, can it be write-back in L2? 2> ...
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25 views

Map a 16Bits to 32 bits address

So, I'm working on a 16 bits CPU Emulator with these settings: Instructions are 4 Bytes long; 24 bits of an instruction are for data purposes, but only 16 bits are used for memory addressing. All ...
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23 views

Calculate the size of memory protection register

One of the methods for virtual memory protection is using a register of accessible pages for every active process. How many bits should the length of this register be, considering: physical memory ...
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64 views

What is difference between parallel virtual machine (PVM) and (mpi) Message passing Interface? [duplicate]

I am using beowulf cluster. And want to know the difference between parallel virtual machine(pvm) and message passing interface(mpi). Thank you.