I'm looking at Transport Triggered Architectures (also this), linked to from an OISC page listing many different 1-Instruction Set Computers. It basically says the following:

TTA programs do not define the operations, but only the data transports needed to write and read the operand values. Operation itself is triggered by writing data to a triggering operand of an operation. Thus, an operation is executed as a side effect of the triggering data transport. Therefore, executing an addition operation in TTA requires three data transport definitions, also called moves. A move defines endpoints for a data transport taking place in a transport bus. For instance, a move can state that a data transport from function unit F, port 1, to register file R, register index 2, should take place in bus B1. In case there are multiple buses in the target processor, each bus can be utilized in parallel in the same clock cycle. Thus, it is possible to exploit data transport level parallelism by scheduling several data transports in the same instruction.

An addition operation can be executed in a TTA processor as follows:

r1 -> ALU.operand1
r2 -> ALU.add.trigger
ALU.result -> r3

The second move, a write to the second operand of the function unit called ALU, triggers the addition operation. This makes the result of addition available in the output port 'result' after the execution latency of the 'add'.

The ports associated with the ALU may act as an accumulator, allowing creation of macro instructions that abstract away the underlying TTA:

lda r1    ; "load ALU": move value to ALU operand 1
add r2    ; add: move value to add trigger
sta r3    ; "store ALU": move value from ALU result

They also link to the Copper Co-processor, but that has 3 instructions. In addition, the above shows how you can create the 3 "macro instructions" from the "move" instruction, so it sort of moves away from a more detailed explanation of the move instruction and how it can be used in a OISC.

The other wiki page also states:

A transport triggered architecture uses only the move instruction, hence it was originally called a "move machine". This instruction moves the contents of one memory location to another memory location combining with the current content of the new location:

move a to b ; Mem[b] := Mem[a] (+, -, *, /, ...) Mem[b]

So from all this I understand that basically the move instruction moves data from one place in memory to another. The memory are the "register files" (which I'm not sure exactly what they are), and this is done by reading and writing from the "transport bus". But already there there are 2 operations (read and write), so I'm confused how this is only actually 1 instruction (a OISC). In addition, I don't see exactly how those r1 -> ALU.operand1 3 "steps" are actually just 1 operation each, I would like to know a little more on what's actually happening.

I'm wondering if one could explain a little more clearly how the move instruction works. How it is only 1 instruction, and how it can do something such as the "ADD" operation or something slightly more complex.