When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. ) Illustrated in timing diagram below. [![enter image description here][1]][1] How is this usually solved (could be different across different CPUs but there are probably trends. ) Is a temporary register used (the "memory address register" could load and output in two separate steps), or is the timing issue just not a problem and tends to work out regardless? Example LDA with two step "memory address register", when LDA_1 => -- Load accumulator from operand addr_in <= dr; state := LDA_2; when LDA_2 => addr_out <= addr_in; state := LDA_3; when LDA_3 => accu <= dr; state := load_opcode; Timing with temporary "address in" register illustrated below, [![enter image description here][2]][2] [1]: https://i.sstatic.net/AGmlx.png [2]: https://i.sstatic.net/tx2sG.png