4 of 4 Original logic diagram was incorrect. Both inputs to an XOR common will *always* yield logic 0 as an output. An inverter is formed by tying one input to logic 1. In this case I also optimised the solution, eliminating an unneeded gate.

Hmmm. It can't be done with boolean algebra that's for sure, but I could wire one up physically. The trick is wiring one of the inputs to a power lead of an XOR gate.

                     I2
                     |
      0  I1          |
      |   |          |
     \|   |/         |
     |\   / |        |
.|---| \ /  |--------/
     \  V  /  
      \   /  
       \ /  
        V 
        |            
     AND OUTPUT

The XOR gate is wired up as a non inverting buffer. The trick involved is that if you wire VCC to GND (or by extension a logic ground), the output is a weak GND.

Disclaimer: this works on the silicon I have, but might not work on all silicon.