Hot answers tagged

5

Computer hardware is fundamentally parallel. Even a modern single CPU core is pipelined, meaning that at the same instant in time, one physical part of the CPU is initiating a fetch of an instruction, another is decoding a slightly earlier fetched instruction, another is calculating the new result of a slightly earlier decoded instruction, and another is ...


3

It's not guaranteed; it may depend on the data. Let's say an 8-way associative cache can hold 8 items at position 512k + j for each fixed j, and a 4-way associative cache can hold 4 items at position 1024k + j. My algorithm accesses locations 1024k + 512 + j for just four values k all over again. And locations 1024k + j for lots of values k, so there is ...


2

I failed to understand @gnasher729 explanation, so this is my one demonstrating the same situation. Let's consider just one line of 8-way cache, and compare it to two corresponding lines (A and B) of 4-way cache. Imagine the situation when we access 4 different addresses of line A, then 5 addresses of line B, repeating that in loop. So, hit:miss ratio for 4-...


1

The cached data might be needed again in the future and keeping it doesn't cause any particular performance problem, so you may as well keep it until you need the space for something else.


1

You first need to establish the access speed of the cache, depending on the cache size (usually larger cache -> slower speed, because of physics). You also need to determine the energy consumption of a larger cache, which will lead to increased heat, which will lead to lower clock speed (again, because of physics). Then you need to find the cost of a larger ...


Only top voted, non community-wiki answers of a minimum length are eligible