Skip to main content
6 votes
Accepted

How does software prefetching work with in order processors?

"In-order" processors only issue instructions in order. Completion is out-of-order even on most processors that are called "in-order". "in-order" just means: if the ...
Wandering Logic's user avatar
5 votes
Accepted

How does a TLB lookup compare all keys simultaneously?

Computer hardware is fundamentally parallel. Even a modern single CPU core is pipelined, meaning that at the same instant in time, one physical part of the CPU is initiating a fetch of an instruction,...
andy_fingerhut's user avatar
5 votes

What does "associative" exactly mean in "n-way set-associative cache"?

An n-way set associative cache is a cache that is chopped up in sections called sets. And each set can hold n-blocks. A cache-address can be broken up up in 3 parts. the offset within the block the ...
pveentjer's user avatar
  • 319
3 votes
Accepted

How does caching, paging, virtual memory, and OS all tie together for UNIX copy-on-write?

It seems like your understanding of the matter is pretty good. You are just missing one tiny trick: Make the pages read-only. When the OS forks the process, it maps ...
Jörg W Mittag's user avatar
3 votes

Does increasing k in a k-way set-associative cache always lead to a better miss rate?

It's not guaranteed; it may depend on the data. Let's say an 8-way associative cache can hold 8 items at position 512k + j for each fixed j, and a 4-way associative cache can hold 4 items at position ...
gnasher729's user avatar
  • 30.7k
2 votes

Does increasing k in a k-way set-associative cache always lead to a better miss rate?

I failed to understand @gnasher729 explanation, so this is my one demonstrating the same situation. Let's consider just one line of 8-way cache, and compare it to two corresponding lines (A and B) of ...
Bulat's user avatar
  • 1,898
2 votes

LRU vs FIFO page replacement

For anyone visiting this thread in the future, FIFO can have less page faults in some scenarios. In this one ( <2, 6, 5, 7, ..., ..., ...> ), it can be completed with 2, 8, 6. The access of 2 ...
Person Giving Answer's user avatar
2 votes
Accepted

Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

No, increasing the memory speed won't help solve the Von Neumann architecture bottleneck. The reason is as memory size is increased the time required to access the memory contents increases. So no ...
Shashank V M's user avatar
2 votes

RAM access time vs cycle time

Cycle time is usually a constant value representing the time between any two clock ticks. This also defines how many operations we can do in the cpu per second. This value is mostly constant, except ...
nir shahar's user avatar
  • 11.6k
2 votes

Problem with cache and memory from university class

If I understand correctly, your directly-mapped cache has 128 cache lines of 8 bytes. So, in a memory address, the 3 least significant bits (bits [0:3]) are used to ...
Charles Bouillaguet's user avatar
1 vote

Assosciative mapping algorithm

Preliminaries In the case of a fully-associative or set-associative cache, there are multiple places where a cache line could be placed, which usually involves evicting an existing cache line. From ...
Pseudonym's user avatar
  • 22.3k
1 vote
Accepted

How to determine the bits of the address used to access the cache?

A direct-mapped cache is another name for a one-way set associative cache. Calculating number of bits in address space ...
Shashank V M's user avatar
1 vote

Query Regarding Direct cache mapping

I am going to talk about the cache - related questions: Block size is $$32 \text{words} = 2^5$$ . That, means that you need, 5 bits for offset. $$\#\text{blocks}=\frac{2^{19}}{2^5}=2^{14}$$, so you ...
tonythestark's user avatar
1 vote

Tag storage when using HBM as an L4 cache

Disclaimer: It's been a while since I last read that book. It was an edition that pre-dated HBM. So I can't really refer to the book to find out what it's saying. The "level" of a cache refers to how ...
Pseudonym's user avatar
  • 22.3k
1 vote

How does a cache handle overwriting between 2 addresses in the same block?

Your program will work exactly as if there was no cache, and as if each single memory operation was completed before the next one is started. Typical implementations will first make sure that the ...
gnasher729's user avatar
  • 30.7k
1 vote

Why do computers keep old cache?

The cached data might be needed again in the future and keeping it doesn't cause any particular performance problem, so you may as well keep it until you need the space for something else.
David Richerby's user avatar
1 vote

design cache system using queuing theory

You first need to establish the access speed of the cache, depending on the cache size (usually larger cache -> slower speed, because of physics). You also need to determine the energy consumption of ...
gnasher729's user avatar
  • 30.7k
1 vote

Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I think i found out the solution, may be helpful for others reading this. The size of a block is 8 bytes. And the memory is adressed with 2 bytes. So each block contains 4 words (considering 1 ...
Muhammed Gül's user avatar

Only top scored, non community-wiki answers of a minimum length are eligible