Questions tagged [computer-architecture]

Questions about the organization and design of computer hardware.

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23 views

A question about Pipeline Cycle

This is my question, I am so confused with my answer, looking for help! This is my answer: However, the instructor said that if an instruction is waiting before ID, the next instruction of IF phase ...
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Help with computer engineering problem

Have been trying to figure out this problem for quite some time but don't know how to approach it. Consider a system that can host 64 GB of memory and has 8MB of L3 cache. Suppose that each cacheline ...
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how worst fit better than best fit?

I am a beginner. I have recently started studying OS. In textbook, it is written as best fit is worse than worst fit. Reason - external fragmentation. IMO,in case of variable partionioning, best ...
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doubt in pipelining

I am not from cse but trying to learn computer architecture on my own. Please clarify the following. In case of pipelining, each stage or subcomponent or subtask is assumed to be done in 1 CPU ...
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12 views

Adding two 4 bit binary numbers into 2 7 Segment LED up to 30 [closed]

I am trying to build a 2 bit binary adder into 2 7 segment LED's up to 30 and I'm having trouble getting passed nine as I believe there need to be an overflow but I am not sure. Was hoping to get some ...
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17 views

Associative mapped cache, word addressable

I have an associative mapped cache with 10 tag bits and an offset of 7bits. What is the size of each main memory block in words(word addressable) and main memory size in words? i worked it out as: ...
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1answer
43 views

What is the difference between a microoperation, microinstruction and control word?

I've seen a few lectures interchangeably use the two words (microinstruction and microoperation). I've found a source that explains the difference between a microoperation and microinstruction, but I ...
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Study of cache behaviour of algorithms on Virtualbox

I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general. I want to understand, is it advisable, if I do this study in an virtualized ...
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9 views

Are there any models of operating systems which don't require rings of privileges, that are also secure?

I am working on a simple operating system in JavaScript and have noticed that there are two kinds of processes: the "main" process (or "kernel" process), and all the other processes. Basically they ...
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1answer
25 views

What happens with register usage in deeply nested functions calls (in theory)?

I am far from being able to construct a meaningful test for this using godbolt or some C compilation tool. But basically I am wondering what it would look like to have deeply nested function calls, ...
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How many registers does a computer *need*?

I read about Why does a processor have 32 registers?, and others. Currently I am messing around with an OS in JavaScript, and wondering how many registers -- or more specifically, how many temporary ...
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8 views

Relationship between associativity, number of sets, block size and cache inclusion policy

I'm studying for an exam and I came across a couple of questions asking me to argue whether cache inclusion is guaranteed or not. I read Wikipedia and wikipedia claims cache inclusion is possible if ...
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2answers
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How does a CPU differentiate between 1-operand instructions and 2-operand instructions?

Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction ...
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Compiler optimization which does an SMT-like optimization in software?

Say I had two functions called one after the other: ...
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3answers
75 views

Is the constant pi (not Raspberry) ever used in general computer science?

Is the constant pi (not Raspberry) ever used in general computer science? If so, how so or when is it applicable?
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What does it mean for a 16 bit processor that issues 24 bit address? [duplicate]

I was solving a problem from William Stallings' 8th edition, in the cache memory section. It was question 4.6, and is as follows: Given the following specifications for an external cache memory: ...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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36 views

Little Endian vs Big Endian?

Suppose a processor uses the big endian representation and x is a 32-bit integer stored in memory starting at the memory address 1000. The memory is byte-addressable, each location holding a byte. ...
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24 views

Read and write ports in a register file?

How many read and write ports in a register file? Moreover, what is the difference between a register and a register file?
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37 views

What is memory model in computer organization?

I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking ...
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28 views

Relation between CPU cycle and Addressing modes

Professor has given this question in exam. I am not able to find relevant reference for this question Which Addressing Modes (for x86 architecture) consumes more CPU cycle?(Consider all are special ...
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What are the smallest and biggest negative floating point numbers in IEEE 754 32 bit?

I am stuck with a question that asks for smallest and biggest negative floating point numbers in IEEE 754 32-bit (their representation and decimal numerical value from which one can approximate the ...
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What is the use of relays in Harvard mark 1 (early electromechanical computer)?

First when I came to know that Harvard mark 1 had relays I thought that the relay were used like today's transistors for the purpose of processing. But I came to know that Harvard mark 1 had 5hp ...
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1answer
34 views

Can a new company make a processor compatible with Windows and current software? [closed]

Would anyone apart from Intel and AMD ever be able to make a processor that can be used on a personal computer, or is it impossible? I believe it is due to them owning the x86 instruction set, which ...
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Is 'the bombe' technically a computer?what is technically meant to be a computer?

Some say that 'the bombe' created by Alan Turing is technically not a computer despite decrypting the codes. Why is it so? Is 'the bombe' technically a computer? First of all what is technically ...
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What is a GPU year?

I am reading papers in machine learning and they say things like, "This computation took $x$ number of GPU years". What is a GPU year? How long is that?
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pipeline processor timing charts and total cycles

There are basically 2 things i need to figure out. Timing charts Total cycles for the 3 mips instructions. How does it differ when it is branch taken and branch not taken for a "predict not taken ...
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Having trouble understanding the use of a label in Assembly

I am currently having trouble understanding what this label means in Assembly as it has no variable size with it. In the following program that declares several variables in the stack offset the ...
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How to create a register from DFF bit components?

I am a new student at computer architectures and my current task is to create a register of 4 bits. We were a working DFF and my bit component seems to work. My DFF: My bit: I tried to create the ...
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44 views

What is a sticky bit in computer architecture?

I am reading about a counter implementation in RISC Architecture. The specification reads, Sticky overflow bit is set when the counter wraps through zero. I can infer that the overflow bit is ...
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1answer
40 views

Lack of Stack Pointer Register

Suppose a processor lacks STACK Pointer Register. But, It does have STACK. Then, in my opinion, a program will still be able to call subroutines but, will be unable to return back from the subroutines....
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3answers
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How can any non-primitive-recursive function like the Ackermann function be implemented on hardware?

If for-loops and function calls both boil down to jump instructions when implemented on a real machine, then how is "The Ackermann function isn't implementable with for-loops" a meaningful phrase?
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L1 Cache Missing Timing Attack

I'm trying to understand Section 3: L1 Cache Missing in the paper Cache Missing for Fun and Profit. I'm stuck on trying to figure out how the covert channel is ...
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14 views

Compare the difference in bus transfer times

Suppose we are given a 2-byte-wide bus that supports single-byte, dual-word (same clock cycle) and burst transfers. The overhead of the single-byte or dualbyte transfer is 1 clock cycle. Now we want ...
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Doubts on Virtually Indexed,Physically tagged Cache

I tried referring a few material (videos on youtube and this link as well), but I still couldn't wrap my head around the concept. My (brief) understanding of the Virtually addressed, Physically ...
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42 views

Least Significant Bit (LSB) vs Little Endian - Are they equivalent in anyway!

For a multiple choice question: What do we call the LSB? (i)Little Endian (ii)Upper bit (iii)Big Endian (iv)Lower Bit I feel ideally none of them is a true correct choice, but my best bet was (...
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Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa [closed]

Can we represent $\sqrt{2}$ exactly even with infinite bits in mantissa in floating point notation or otherwise. We actually have to prove this is not possible. But why can't we if we have infinite ...
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1answer
41 views

Why does arithmetic left shift of negative number leads to positive number?

According to this Wikipedia article, when arithmetic left shift operation is applied to a signed number, the number is multiplied by 2. But there are certain situations where a negative number becomes ...
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1answer
42 views

Software management of TLB misses?

I'm reading an OS textbook and it was talking about TLB misses being handled by software. I'm very new to all this by the way. So there's a context switch to some kernel procedure. But surely in this ...
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27 views

Cache mapping calculation

A cache has following specifications: Block size = 16 Bytes Set size = 2 way set associative Number of sets = 128 Physical address = 23 bits, byte addressable My Questions are: 1) How many blocks ...
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100 views

AMAT using Local miss rate, global miss rate, local hit rate, global hit rate

Consider the following scenario as shown in image: I have summarized the above Memory layout in terms of Miss rates and hit rates: ...
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1answer
67 views

Can a CPU be replaced without interrupting the processes running on it?

When I need to replace the CPU of my computer, I turn it off, replace the hardware, then reboot it. But what if you need to replace the CPU (in a single CPU machine) without stopping the processes ...
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Need help understanding set-associative cache

The problem I'm trying to solve is: A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main ...
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Does the Hack computer from “The Elements of Computing Systems” use Von Neumann architecture?

I'm reading "The Elements of Computing Systems" (subtitled "Building a Modern Computer from First Principles - Nand to Tetris Companion) by Noam Nisan and Shimon Schocken. Chapter 4 is about machine ...
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Regarding Amdahl's balanced system law

One of the paper titled "Rules of Thumb in Data Engineering" (Jim Gray et. el.) mentions some calculations based on Amdahl's balanced system law. Link to paper: https://www.microsoft.com/en-us/...
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Why is there no extensive Standards Body overseeing ISAs, Bitcodes, Code Representation, etc… as there is in the case of Unicode

There exist a vast array of prominent bitcode formats, each suited for their specific task: LLVM IR: This format is build around a XML like binary streams model, designed to be used as a common ...
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1answer
127 views

Create NOT gate from other gates

If we are given only one NOT gate and any number of OR and AND gates, then, can we simulate more NOT gates?
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Is the control bus “measured” in the number of bits it have?

In the system bus, the data bus and the address bus are "measured" in the number of bits that they have, for example we may say that the data bus is 32-bit and the address bus is 32-bit for some CPU ...
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Does RAM take the copy of the program or does it load programs from the hard disk?

I guess it copies, since it is a temporary memory, it will erase if power is not supplied, so, that will lead to data loss right, but still, I need clarification.