3

The answer provided by @Benjoyo is not accurate. The CPU clock can be lower than the system clock, at least in microcontrollers. As seen in this link, the PIC microcontrollers have the CPU clock, with a rate of $f_{cy}$ (also called instruction cycle frequency), and the system clock, with a rate of $f_{osc}$ (oscillator frequency). Physically, what ...


2

Along with the problem of unpredictable T/NT patterns (as explained by the other posts), there is a problem with the return addresses. The prediction of the return address is done by using the RAS (return address stack), which is a circular buffer containing the last called addresses. When a return instruction is used, the last address of the RAS is used ...


2

It depends. If it's a lot of data and a little bit of computation, yes, there is no net savings. If it's a little bit of data and a lot of computation, no, there is a net savings. It all depends. Normally a GPU is used for situations where the amount of computation time saved greatly outweighs the time to transfer the data -- such as training machine ...


2

There's cache misses when you access a page for the first time, then you get hits. Since the kernel initialises the page, it gets all the cache misses. Then it passes the page to the user code, which gets cache hits. The same misses would happen in user code if the kernel didn't initialise the page.


1

I don't know how old your book is, but some architectures (I know of the early SPARCs, there may be others) only had 32 bit floating point registers. Double precision instructions used pairs of registers for storage. This became much less common on general-purpose hardware when 64-bit integer registers became the norm. If anything, we have the converse ...


1

It would be good to have as much as we got RAM, because RAM is slow and registers are blazingly fast. Registers are expensive and RAM is cheap (per bit), so we got what we got -- some registers and cache to fight RAM latency. Some people may say, that it won't be good if all RAM was replaced by register memory, because to address these registers we would ...


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