# Tag Info

105

Addition is fast because CPU designers have put in the circuitry needed to make it fast. It does take significantly more gates than bitwise operations, but it is frequent enough that CPU designers have judged it to be worth it. See https://en.wikipedia.org/wiki/Adder_(electronics). Both can be made fast enough to execute within a single CPU cycle. They'...

98

Computers have a "real-time clock" -- a special hardware device (e.g., containing a quartz crystal) on the motherboard that maintains the time. It is always powered, even when you shut your computer off. Also, the motherboard has a small battery that is used to power the clock device even when you disconnect your computer from power. The battery doesn't ...

83

First, not all processor architectures stopped at 32 registers. Almost all the RISC architectures that have 32 registers exposed in the instruction set actually have 32 integer registers and 32 more floating point registers (so 64). (Floating point "add" uses different registers than integer "add".) The SPARC architecture has register windows. On the ...

77

A byte of data is eight bits, there may be more bits per byte of data that are used at the OS or even the hardware level for error checking (parity bit, or even a more advanced error detection scheme), but the data is eight bits and any parity bit is usually invisible to the software. A byte has been standardized to mean 'eight bits of data'. The text isn't ...

55

if you ran an electrical current through a material today, it would travel at the same speed as if you did it with the same material 50 years ago. With that in mind, how is it computers have become faster? What main area of processor design is it that has given these incredible speed increases? You get erroneous conclusions because your initial ...

48

There is a general historical trend. In the olden days, memories were small, and so programs were perforce small. Also, compilers were not very smart, and many programs were written in assembler, so it was considered a good thing to be able to write a program using few instructions. Instruction pipelines were simple, and processors grabbed one instruction ...

48

Traditionally, a byte can be any size, and is just the smallest addressable unit of memory. These days, 8 bit bytes have pretty much been standardized for software. As JustAnotherSoul said, the hardware may store more bits than the 8 bits of data. If you're working on programmable logic devices, like FPGAs, you might see that their internal memory is often ...

47

This is a broad question that does not have an easy answer; it's a long way from electrons skittering along copper wires to rendering a website in Firefox. I will attempt to give you an overview from bottom to top and point you towards the right things to look up. Encoding Numbers The basic motivation is to compute things, as in doing arithmetics¹. The ...

46

Assembly language is a way to write instructions for the computer's instruction set, in a way that's slightly more understandable to human programmers. Different architectures have different instruction sets: the set of allowed instructions is different on each architecture. Therefore, you can't hope to have a write-once-run-everywhere assembly program. ...

44

That depends both on the processor (not just the processor series, it can vary from model to model) and the operating systems, but there are general principles. Whether a processor is multicore has no direct impact on this aspect; the same process could be executing on multiple cores simultaneously (if it's multithreaded), and memory can be shared between ...

39

Let me see if I can clear up a few potential misconceptions here. Sometimes people think that when they write a research paper they have to use fancy language: it's not enough to just say what they mean, but rather, it has to be written in academic code with more complex-sounding language. Or, they think that using bigger words will make them sound more ...

38

There are several aspects. The relative cost of a bitwise operation and an addition. A naive adder will have a gate-depth which depend linearly of the width of the word. There are alternative approaches, more costly in terms of gates, which reduce the depth (IIRC the depth then depend logarithmically of the width of the word). Others have given ...

38

The best answer I can give is, it doesn't really "look" like anything. The instruction currently being executed by the CPU is represented by a series of wires, some of which have a high voltage, some of which have a low voltage. You can interpret the high and low voltages as zeroes and ones, but you can equally well interpret groups of high and low voltages ...

32

That text is extremely poorly worded. He is almost certainly talking about ECC (error-correcting code) RAM. ECC ram will commonly store 8-bits worth of information using 9-bits. The extra bit-per-byte is used to store error correction codes. (In both cases, every byte is spread across every chip. Image courtesy of Puget Systems) This is all completely ...

31

First your integer numbers are converted into binary numbers. For example, the integer 2 is converted to 0010. The CPU uses a digital comparator: A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than or less than or equal to the ...

31

Since we're in Computer Science, I'll answer this way: they don't. What do we mean by a "computer?" There are many definitions, but in computer science as a science, the most common is the Turing machine. A turing machine is defined by several aspects: a state-set, a transition table, a halting set, and important for our discussion, an alphabet. This ...

29

Memory latency is one of the fundamental problems studied in computer architecture research. Speculative Execution Speculative execution with out-of-order instruction issue is often able to find useful work to do to fill the latency during an L1 cache hit, but usually runs out of useful work after 10 or 20 cycles or so. There have been several attempts to ...

27

That means, one year of computation time on a single GPU (or half a year on two GPUs, or a quarter of a year on four GPUs, etc.). If you are thinking of using this term in your own writing, I encourage you to also specify what type of GPU you are using. One-GPU year on a Tesla V100 GPU is a lot more computation than one-GPU year on a K520 GPU. The notion ...

25

The complete picture is fairly complicated. There are many layers built on top of one another that collectively implement high-level abstractions on top of electrical voltages. There is no simple explanation of how everything is put together, especially considering that computer hardware and software has evolved dramatically in the past fifty years. If ...

25

It can be software, or hardware, or both, or none. There are two kinds of overflows: overflow when growing the stack (when entering a function), and overflow when accessing an array on the stack. Overflows when growing the stack can be detected by making a bounds check on function entry, to verify that there is enough room (and either signal an error or ...

24

CPUs operate in cycles. At each cycle, something happens. Usually, an instruction takes more cycles to execute, but multiple instructions are executed at the same time, in different states. For example, a simple processor might have 3 steps for each instruction: fetch, execute and store. At any time, 3 instructions are being processed: one is being fetched, ...

23

I think I see your confusion. The TLB and the data cache are two separate mechanisms. They are both caches of a sort, but they cache different things: The TLB is a cache for the virtual address to physical address lookup. The page tables provide a way to map virtualaddress $\mapsto$ physicaladdress, by looking up the virtual address in the page tables. ...

23

Some other things to consider: Part of the reason for using a binary number system is that it's the lowest-base number system that can represent numbers in logarithmic, rather than linear, space. To uniquely distinguish between $n$ different numbers in unary, the average length of representations must be proportional to at least $n$, since there is only ...

20

The question as stated is not quite answerable. A word has been defined to be 32-bits. We need to know whether the system is "byte-addressable" (you can access an 8-bit chunk of data) or "word-addressable" (smallest accessible chunk is 32-bits) or even "half-word addressable" (the smallest chunk of data you can access is 16-bits.) You need to know this to ...

20

None of the above. As you noted, DMA and demand paging can be useful features but are not necessary to support multiple users and multiprocessing. Address translation is not necessary even for memory protection. Memory protection can be separated from address translation via a protection lookaside buffer or memory protection unit. Providing a distinct ...

19

Here are a few papers that talk about the cache implications of generational garbage collectors: Caching Considerations for Generational Garbage Collection The Effect of Garbage Collection on Cache Performance From what I can gather, the primary issue is that garbage collected systems trade off space in memory to avoid up front collection. The same thing ...

19

The system clock is needed to synchronize all components on the motherboard, which means they all do their work only if the clock is high; never when it's low. And because the clock speed is set above the longest time any signal needs to propagate through any circuit on the board, this system is preventing signals from arriving before other signals are ready ...

18

I am by no means an expert on this topic, but just from casually reading Wikipedia: it relies on the motion of spherical billiard balls in a friction-free environment made of buffers against which the balls bounce perfectly ... this sounds very realistic. Nobody has actually figured out how to actually make such gates yet, they're merely of theoretical ...

17

Just two more reasons for limiting the number of registers: Little gain to be expected: CPU such as current Intel/AMD x64 models have 32kByte and more of L1-D cache, and access to the L1 cache usually takes only one clock cycle (compared to about a hundred clock cycles for a complete single RAM access). So there is little to be gained from having more data ...

17

Generally speaking, the short answer is that a byte is 8 bits. This oversimplifies the matter (sometimes even to the point of inaccuracy), but is the definition most people (including a large number of programmers) are familiar with, and the definition nearly everyone defaults to (regardless of how many differently-sized bytes they've had to work with). ...

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