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That means, one year of computation time on a single GPU (or half a year on two GPUs, or a quarter of a year on four GPUs, etc.). If you are thinking of using this term in your own writing, I encourage you to also specify what type of GPU you are using. One-GPU year on a Tesla V100 GPU is a lot more computation than one-GPU year on a K520 GPU. The notion ...

4

There are many advantages to memory mapped I/O Access: Memory mapped devices use the same instructions/addressing modes as regular memory. These map well into high level languages allowing device drivers to manipulate devices without the need to drop down into assembly language to use special I/O instructions. Security: As memory addressed devices, memory ...

4

ALU-less computers are certainly possible. The 1 Square Inch TTL CPU project on hackaday.io by roelh is able to circumvent the need for an ALU using lookup tables! Furthermore, the project also says the HP9100 calculator uses a similar technique. THERE IS NO ALU NO ALU... I could have programmed a small PIC or AVR as ALU (Wikipedia: ALU), but ...

4

LSB (least significant bit) and MSB (most significant bit) apply purely to the values of an integer. The least significant bit is the bit with value 1, the second least significant bit is the bit with value 2, and so on. "Little endian" and "Big endian" are just artefacts from the fact that the bytes of a number can be accessed individually as they are ...

4

Real machines have access to a stack, and so can implement recursion. This is all that is needed to implement the Ackermann function. However, the Ackermann function grows very fast, so you would only be able to calculate a few of its values given realistic time and space constraints.

3

With such an instruction set, all you could express are straight-line programs. Without branches, you can't have loops. Thus, the program would not be able to handle arbitrary-length inputs: it would be limited to dealing with fixed-size inputs (or inputs with a fixed known upper bound on the size of the input). So, that wouldn't be very satisfactory.

3

Picture hanging can realize any monotonone boolean function. I.e., you can hang a picture using two pins so that it falls IFF both pins are removed. This is trivial to achieve, and realizes an AND gate. However, you can also hang it so that it falls IFF either pin is removed. Implementing this OR gate is not so trivial at first. See the linked paper for ...

3

It's not guaranteed; it may depend on the data. Let's say an 8-way associative cache can hold 8 items at position 512k + j for each fixed j, and a 4-way associative cache can hold 4 items at position 1024k + j. My algorithm accesses locations 1024k + 512 + j for just four values k all over again. And locations 1024k + j for lots of values k, so there is ...

3

Actually, it has been done: https://en.wikipedia.org/wiki/Lisp_machine One aspect in CPU design for FP is garbage collection. GC is very important for functional languages. Common implementations require that the GC can distinguish between pointers and non-pointer data. Effectively, that means storing an extra bit along your data. This is the reason that, ...

3

The answer provided by @Benjoyo is not accurate. The CPU clock can be lower than the system clock, at least in microcontrollers. As seen in this link, the PIC microcontrollers have the CPU clock, with a rate of $f_{cy}$ (also called instruction cycle frequency), and the system clock, with a rate of $f_{osc}$ (oscillator frequency). Physically, what ...

3

Addressing the core of your question, instructions are typically stored in a format that requires some translation (decoding) to become the control signals for instruction execution. Requiring some decoding presents an abstraction layer between the hardware and the software, allowing the control signals used for execution to be changed without breaking ...

3

Go to Agner manuals page and download them all, you will find tons of interesting info there. In particular, microarchitecture.pdf says There is a false dependence between memory addresses with the same set and offset, i.e. with a distance that is a multiple of 4 Kbytes: ;Example 9.6. Sandy bridge false memory dependence mov [rsi],eax mov ebx,[rsi+1000H]...

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Consider a circuit having a single NOT gate, computing some function $f(x)$. We can write $f(x) = g(x,\lnot h(x))$, where $g,h$ are monotone functions. Consider now a sequence of inputs $x_0 < x_1 < \cdots < x_n$ (i.e., $x_0$ is the zero input, and $x_i$ is obtained from $x_{i-1}$ by changing one bit from 0 to 1). Since $h$ is monotone, it is ...

3

A full answer to this question depends on the underlying computer architecture, as well as on layers of protection that the operating system may add on top of the basic architecture. In the Harvard architecture instructions and read/write data are held in physically separate memory stores accessed by separate data pathways (buses). It is physically ...

3

It doesn't. The CPU executes instructions beginning at the program's start address. After each instruction, the CPU either jumps to the address specified by that instruction or, if it's not a jump, moves on to the next instruction in memory. The start address is known to contain executable code because the program was just loaded there. The correctness of ...

3

In current architectures, the CPU does not need to distinguish. Whatever is pointed by the program counter register will be interpreted as an instruction and executed. Everything else can be manipulated as "data". For example, you can have a program modify its own code (in fact, some computer viruses do this, with the aim of avoiding detection).

3

The phrase "The Ackermann function isn't implementable with for-loops" is shorthand for "The Ackermann function $A(m,n)$ cannot be implemented using bounded for-loops where an upper bound on the number of iterations in each loop is determined in advance from the values of the parameters $m$ and $n$". In other words the Ackermann function is not primitive ...

3

A sticky overflow bit means that the next operation that does not overflow (but would set the bit if it did) will not clear the bit. The value is sticky/persistent and must be cleared to detect newer overflows.

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A "register file" is an aggregation of registers. That is, it is one component that holds several different registers. How many read/write ports? Well, this depends. It can be 1 and 1, or more, according to the specific system. If you are the engineer, you can design a register file with as many read and write ports as you desire. The maximal number would ...

3

You need to make your question a bit more precise. First, regarding your request to avoid "unlimited" registers -- I assume you mean registers that can hold an arbitrary value (e.g., any natural number). If you a-priori bound your registers, then the possible states your machine can be in is finite. That is, you have a deterministic finite automaton (or ...

3

There are two possibilities: No operation is allowed to take longer than one clock cycle. If the designers of the CPU can't fit an operation into one clock cycle, then either the clock cycle must be made longer, or that operation must be split into two, or they designers work extra hard to make that operation faster. That's the more common way to do this. ...

2

Along with the problem of unpredictable T/NT patterns (as explained by the other posts), there is a problem with the return addresses. The prediction of the return address is done by using the RAS (return address stack), which is a circular buffer containing the last called addresses. When a return instruction is used, the last address of the RAS is used ...

2

There are dozens and dozens of stack machines out there in the wild, and they all have different instruction sets. So there's no single correct answer. Some people might consider using CALL like that cheating: after all, it relies on things like ADD and CMP and JMP and DUP and such all being implemented in the machine, so why don't you call them ...

2

I failed to understand @gnasher729 explanation, so this is my one demonstrating the same situation. Let's consider just one line of 8-way cache, and compare it to two corresponding lines (A and B) of 4-way cache. Imagine the situation when we access 4 different addresses of line A, then 5 addresses of line B, repeating that in loop. So, hit:miss ratio for 4-...

2

Two bits for the register and ten bits for the address makes sense when you have ~four registers and ~1024 words of memory. Any more and you can't address it all (how would you access register #5, or memory address #1025?); any less and you're wasting precious bits in every instruction (why use two bits for the register when there's only two registers to ...

2

A buffer is usually used only as temporary storage while something is being transmitted or read. For instance, you might be reading data from a slow-response external storage medium (e.g., a CD) and processing it continuously. In this setting, the first process reads chunks of data from the medium and writes it to the buffer on demand, while the latter reads ...

2

Buffer is a concept. It's a structure used to hold data to keep it "closer" while you're processing it. Like buffering a YouTube video. Many types of memories are used as buffers. RAM is certainly great for holding buffers, but for large data you can also buffer data on a hard drive, or an SSD. Buffers are mainly used to hold data that is costly to read ...

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Buses usually connect the central processing unit (CPU) with peripheral devices, like memory or other Input/Output devices. To activate a memory you need to do two things: - specify the cell in the memory you want to write to / read from (that would be the address) - give the data to write to the memory, or take the data from the memory (this information ...

2

What you are looking for is named "address decoding". If a processor can address 64kB, its address bus is something like A[15:0]. If you use a 1kB memory chip, its addresses will be A[9:0]. There are several options : Either you don't connect the bits A[15:10] of the processor. The memory will be mirrored at several "places" in the CPU address map, in ...

2

Code isn't arranged randomly in memory. The next instruction to be executed will, by default, be the one at the next memory location, unless something specific (a "jump" instruction) is done to execute code from somewhere else. So, if your program is literally "Do A, then B, then C, then D, then E", the compiler will place those instructions in consecutive ...

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