New answers tagged computer-architecture
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The CPU
What is important to understand is that the CPU comes with a predefined instruction set that it can handle. For example, x86-64 CPUs have a defined set of instructions that they can operate on.
The CPU has a data bus and an address bus. The buses are only pins under the processor and they are connected to metallic lines that are directed towards the ...
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It's not clear to me how to interpret "can be considered", so I'm going to identify one technical question that can be answered.
Given a FSM $F$ and an input sequence $S$, it is possible to build another FSM $F'$ so that the execution of $F'$ on the empty input is in one-to-one correspondence with the execution of $F$ on $S$ (and in particular, ...
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The answer is A and D.
The 16 bit values are printed by the LE machine. The extra 255 is visible.only on the big endian machine.
The question could have been made more confusing by inducing doubt about nibble (4 bit) location, but the teacher carefully avoided all ambiguity by using a difference where two consecutive nibble are identical.
In other words, 255 ...
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Basically, it is the data bus between the processor and the RAM that does this conversion from logic state to real voltage that can be measured with an instrument like a scope and logic analyzer.
Modern computers are difficult to design and verify because the frequency is so high, the voltages decreased to lower values such as 3.3 volt or 1.8 volt. ...
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The microprocessor has to read an I/O port that is connected to the mouse or track pad.
The information is probably using more than one byte (8 bit) or one 'word' (32 bit), so the processor either read the same port many times or has other way to get the position of your fingers on the device.
The information must be saved in RAM because the internal memory ...
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You can calculate the speedup in MFLOPs. Speedup is a dimensionless quantity, so you don't need to know the execution time to calculate it.
You need to know the old execution time only if you need to find out the improved execution time.
In this problem, we can calculate the increase in MFLOPS by dividing the ratio of Floating point instructions to total ...
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What you are looking for is called an Application-Specific Instruction-Set Processor (ASIP), here hardware and software is co-designed using an ASIP Design tool. Here is an open-source ASIP Design tool: https://github.com/cpc/tce
One can choose between implementing logic (sequential or combinational) as software, hardware or ASIP on an FPGA based on this ...
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This is a complex matter. To begin with, when you move your mouse, there is so much going on at once, that I cannot even begin to explain everything here. So, I will focus on the most fundamental thing: How does the computer actually compute?
As you are probably familiar with, computers have memory called RAM, and a CPU that is able to execute "commands&...
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In a processor that would nowadays be considered simple, you need two numbers for an instruction: what is the total execution time (for example 4 for load) and how long you need to wait before another independent operation can be issued - it seems that someone assumed 1 cycle between instructions for load. A different processor might only allow a load every ...
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2,3 is answer.
If you split hex number into bytes..
In hexa representation, each digit corresponds to 4 binary digits....
(I.e 2 hex digits =8 bits= 1 byte).
If little endian representation is
(byte-n).....(byte-2)(byte-1) then
Big endian representation is
(byte-1)(byte-2).....(byte-n)
With in the byte no change in bit sequence.
A) 0x0001
Little endian ...
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The way the question is framed, I do not agree with the concept at all.
A number is after all a number, be it big endian or little endian.
The main concept of Big endian or little endian is as follows:
Big Endian: In computer system which is big endian, the lower order byte of the data in the memory maps to the higher (big) order byte of the registers in ...
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If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer
According to the dictionary, the definition of "numerical value" is "a real number regardless of its sign", in other words absolute value. Since the integer is unsigned, its numerical value is itself, and that ...
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If you are decoding instructions using logic based on individual bits in the opcode, this "inversion' scheme is probably counter productive. If the opcodes are decoded using a simple table lookup of the "value" of the opcode, then the actual pattern of the opcode is just arbitrary and the inversion scheme is just as valid as one based on the ...
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What’s interesting is that you don’t even need to know how bigendian and littlendian numbers are stored in memory, just that they are stored in opposite order!
Assume that two bytes aa and bb are stored in memory, and interpreting these bytes as a littleendian 16 bit integer gives a value of 0xaabb = 256a + b. Interpreting the same two bytes as bigendian ...
1
In little endian, the least significant byte is the first you read. It means that 0x6665 (LE) should be read as
$$0\text{x}6665 \text{ (LE)} =(0\text{x}66) + (0\text{x}65) \times 256 = 102 + 101\times256 = 25958$$
If you read 0x6665 in big endian, you read the most significant byte first, and you get :
$$0\text{x}6665 \text{ (BE)} = (0\text{x}66) \times 256 +...
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I think part of the reason was that the DEC VAX 780. Dec DG's main competitor had beaten DG to the creation of a 32 bit minicomputer. However Dec handled backwards compatibility with an inelegant kludge. In the early Vax there was an embedded PDP-11 (the Vax's 16 bit ancestor), switching between PDP-11 mode and Vax 32 bit mode was literally switching between ...
1
The machine with 2 threads per core will have always have more throughput than a machine with a single thread per core. A machine with more threads will be able to execute more threads concurrently and it reduces the idle time spent by a CPU's resource (example: Arithmetic Logic Unit). It does this by switching to a different thread if the current thread is ...
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There's no real way to answer this without a lot of details about both the code to be executed, and the micro-architecture of the CPU executing the code.
A CPU that can execute multiple threads per core will typically start with a pool of instructions, decoded and ready to execute. As instructions enter the pool, a scoreboard1 gets updated to reflect inputs ...
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The offset should be 4 bytes, since 1 byte is 8 bits and 32 bits contain 4 bytes.
1
In the most common usage, and in particular in IEEE-754, machine epsilon is the smallest number $\epsilon$ such that $1 + \epsilon \ne 1$.
It does have an interpretation in terms of relative distance between numbers: It is the largest relative separation of two consecutive normal numbers.
There are a couple of important points to understand here:
This is ...
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This reply was stored in RAM on your computer as part of the mechanisms involved in you reading it.
It is very definitely not written in machine code. I don't even know what the machine code of your computer is.
Fundamentally, RAM stores bits. The meaning of the bits is not inherent in the bits. These particular bits are used as data to some software that ...
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In part a same processor is assumed, and 2 compilers are used. In part b, 2 processors with different clock frequency is used, since the execution times for both processors are equal but the CPIs and dynamic instruction counts are unequal. The CPI for both processors is the same as the CPI from part a because the same compilers were used and the same ...
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Only the number of instructions would be the same. Clock Rate, CPI, Execution time and MIPS depend on the micro-architecture (also known as hardware architecture).
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Same ISA means they understand the same instructions in binary. They can certainly be very different in speed. Look at e.g. the x86 family (disregard the instructions added over time). The very latest Pentium is certainly much faster than the first 386, and even within each "number" there are variations.
Even crasser, remember ye goode olden days ...
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I’m afraid you are looking at things from the wrong level. There’s a highest level that we usually look at here: Algorithm design. Next level: High level programming languages. Below that: Assembly languages and machine code. Below: Processors. Below that: Logic design. Building things from and/or/nand gates. Out Next level: Transistors. And that’s where ...
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