New answers tagged computer-architecture
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I think that the question has no clear answer. Data can be transferred in a synchronous or asynchronous manner. Each has its own pros and cons. Synchronous communication is irrelevant for some systems, e.g., when there is no joint clock or where the distance causes too large clock skews. Both methods are capable of transferring large amounts of data. For ...
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There are many techniques that can be applied.
At a higher level you have 2 main options:
ILP: Instruction Level Parallelism
TLP: Thread Level Parallelism
So increase parallelism in a single instruction stream or increase parallelism due to having multiple instruction streams.
Multicore (SMP) and hyperthreading (SMT) help to increase parallelism in ...
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An n-way set associative cache is a cache that is chopped up in sections called sets. And each set can hold n-blocks.
A cache-address can be broken up up in 3 parts.
the offset within the block
the index that identifies the set
the tag that identifies the block in the set.
When a request comes in, the index is calculated to identify the set. Then the tags ...
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The straightforward algorithm is more complicated than the straightforward algorithm for multiplication. For addition, you need to compare the exponents, shift the mantissa of the operand with smaller exponent, add or subtract (the signs might be different) and then check for overflow or check for an unnormalised result. Lots of complicated steps.
For ...
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Modern x86/x64 CPUs are incredibly complicated. There can be dozens of instructions in various stages of execution flying around a CPU core at a given time. The cycle boundaries are just times when the various functional units synchronize with each other and work out what each one will be doing next.
A CPU can be made faster at the same clock rate by ...
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If executing each instruction took a single clock-cycle, then your confusion would have been understandable, as a higher clock frequency would imply shorter cycle time, hence, more instructions per unit time.
However, the reality is quite different. Modern CPUs are usually pipelined, meaning that a single instruction takes multiple number or core-clocks, and ...
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This is multi-cycle processor, where each stage takes a single clock cycle. The text suggest that the new MEM stage should take 2 clock cycles. Then, it can be seen as splitting this 2-cycle stage into 2 separate 1-cycle stages which we can call MEM1 and MEM2 respectively.
There is no new input. You only need to make sure that the "right" input ...
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A stack is a last-in-first-out structure. This causes the reverse order you experience. What you need is a first-in-first-out structure, i.e., a queue.
This way or another, the stack in x86 is just a region in the memory you can access directly. Instead of popping each digit, initialize BP to point at the bottom of your stack (the first digit), then print it,...
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As part of the instruction decode phase, the operands are fetched for the instruction. In a very naive pipeline implementation, the operands for read will only be visible after the write instruction has written back its changes to the internal registers (so the last stage).
To prevent such long stalls, a CPU can apply tricks like forwarding the store to the ...
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It is used for:
Image analysis, and specially face recognition and search photos library.
Language detection, text recognition and analysis ( to identify concepts in a text ). Used for advanced search in text
Speech recognition
Sound analysis, for efficient filtering and removal of noise in conversations and sound recognition ( Be able to differentiate ...
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My understanding is that a write-miss occurs when we want to write data to a location in main memory whose data is not currently in its corresponding cache block.
This is similar to a read miss: if the cache block that a memory location is mapped to does not contain the data of that memory location (indicated by differing tags), then some other memory ...
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The max delay isn't 200 and 350. In both cases, there is also a stage with a delay of 400ps, the clock speed is limited by that stage as well. The clock speed cannot be faster than 1/400ps = 2.5GHz either way, otherwise the slowest stage would break.
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This is different for any processor. You should consider going to the Intel, ARM and AMD websites and looking for the right manuals. That’s what I would do if I had to answer the question, and that’s what I recommend you should do.
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