New answers tagged computer-architecture
1
vote
Accepted
Function of data pin(s) in a single RAM chip
Each address in this RAM chip stores 4 bits. For example, you can write data 0100 to address 01010101010101010101 and then write data 0011 to address 00000000001111111111 and then read address ...
0
votes
What do "JAMZ", "JAMN", and "JMPC" stand for in Mic-1?
From this reference: http://wtkrieger.faculty.noctrl.edu/csc220_winter2014/lecture/note22.pdf,
12 bits control the selection of the next microinstruction:
Addr (9 bits) - the address of the next ...
2
votes
RISC-V execution model
In the terminology that you're using, RISC-V is a register-register ISA.
For integer and floating point instructions:
All arithmetic and logic operations take registers as operands and write the ...
0
votes
Assosciative mapping algorithm
Preliminaries
In the case of a fully-associative or set-associative cache, there are multiple places where a cache line could be placed, which usually involves evicting an existing cache line.
From ...
Top 50 recent answers are included
Related Tags
computer-architecture × 1090cpu × 146
cpu-cache × 128
memory-hardware × 92
operating-systems × 85
cpu-pipelines × 75
memory-access × 57
memory-management × 50
terminology × 33
mips × 33
arithmetic × 32
parallel-computing × 30
virtual-memory × 28
digital-circuits × 24
logic × 22
compilers × 21
cache × 21
assembly × 17
algorithms × 16
floating-point × 16
programming-languages × 15
performance × 15
turing-machines × 14
computation-models × 13
memory-allocation × 13