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4

1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only. For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (...


3

Go to Agner manuals page and download them all, you will find tons of interesting info there. In particular, microarchitecture.pdf says There is a false dependence between memory addresses with the same set and offset, i.e. with a distance that is a multiple of 4 Kbytes: ;Example 9.6. Sandy bridge false memory dependence mov [rsi],eax mov ebx,[rsi+1000H]...


2

This is the kind of case where all you need to do is to find and follow the definitions. There is nothing more you need to know semantically. What is actually happening in the physically world should be (roughly) clear to you. It is a question about how we translate the our understanding using appropriate, generally accepted terminologies. It is a question ...


2

CPU registers are often counted as part of primary memory (since they are directly accessed by the CPU - see Wikipedia) and are often volatile, so it seems likely that the expected answer is (1). However, this is one of those annoyingly ambiguous questions which depend on the student memorising a very specific set of definitions and ignoring any exceptions.


2

Cache lines always start at a byte address that is a multiple of the cache size, like 0, 64, 128 etc. If you need 8 bytes starting at byte 30, then the cache line containing bytes 0 to 63 will be loaded. If you need 8 bytes starting at byte 60, then you need bytes from two cache lines, so the cache line from byte 0 to 63 is loaded, then the line from byte ...


1

"Cache miss penalty" would be the extra time that is spent because of the cache miss. Let's say your L1 cache has 5 cycles access time, and L2 cache has 23 cycles access time. That doesn't tell us enough yet. A clever implementation might immediately detect that there is a cache miss, and send the data from the L2 cache simultaneously to the L1 cache and ...


1

It appears that the analysis assumes that integer variables are stored in registers, whereas array elements have to be loaded from and stored to memory. The point you've missed is that the statemnt X += Y requires reading X and then writing the new value of X. sum += a[i][k] * b[k][j]; This loads a[i][k], loads b[k][j], multiplies them, reads sum, adds sum ...


1

OK, you can read CPU specs and write ASM program exploiting all their features. It's OK and will work as far as you don't change your hardware :) Now, when you start to write C (or any other high-level language), you no more spoke to hardware specs, you spoke to the language specs. According to C specs, this code: bool found = false; while(!found); may ...


1

There are at least three aspects to consider. And you are looking at only one of them. The first aspect is transformation from the programming language to the machine language. A compiler is allowed to do a lot of things which may not be intuitive. And if it is not aware that you want an atomic variable, it may avoid to generate the instructions you ...


1

This is very simple actually, and has nothing to do with hardware whatsoever. If you have a variable static bool b; and some code b = true; dosomething(); b = false; dosomethingelse(); b = true; If the compiler can figure out that dosomething() and dosomethingelse() don't read or write b, then the compiler is not required to generate code for the ...


1

The following possible uses come to mind, though I am not aware of any academic exploration of these ideas. Way Dueling One possible use is to extend the range of set-dueling. Presented in Moinuddin K. Qureshi et al.'s "Adaptive Insertion Policies for High Performance Caching" (2007), the "Set Dueling mechanism dedicates a few sets of the cache to each of ...


1

It's back to the mechanism of cache. When the cpu wants a data in cache, try to read data from cache. If there is the data in cache, It will fetch data from cache. This time of reading data from cache (the different between the speed of cache memory and register!) will be denoted by Hit time. If the wanted memory in the related instruction does not exist ...


1

Advantages The advantages of larger block size include: smaller tag storage (or larger cache capacity for a given tag storage budget), greater bandwidth efficiency, memory error correction code efficiency, potentially improved way prediction/memoization, potentially larger access bandwidth, effective prefetching under sufficient spatial locality in the ...


1

The straightforward manner of indexing and tagging a cache is for the index to be the address (in blocks, i.e., removing the block offset) modulo the way size (in blocks) and for the tag to be the quotient of these numbers. The computational cost of exact division for non-powers-of-two makes this less practical for first level caches, but Mersenne number (2n-...


1

There are several issues involved in this design decision. Since conventional DRAM does not support finer-grained write enable (graphics memories often do), when the data was eventually written back if an entire memory access chunk (often cache block sized) was not written then a read would be necessary. Since conventional DRAM interfaces have significant ...


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