2

There's cache misses when you access a page for the first time, then you get hits. Since the kernel initialises the page, it gets all the cache misses. Then it passes the page to the user code, which gets cache hits. The same misses would happen in user code if the kernel didn't initialise the page.


2

If it is implemented in hardware, prefetching is typically done asynchronously. It's also possible for a compiler to insert extra prefetch instructions into the code. Thus, the initiation of the fetch is done synchronously, but then the memory access continues asynchronously. See https://en.wikipedia.org/wiki/Cache_prefetching.


2

RAM just gets requests for data to move to/from the CPU (really the MMU). Data is moved in units of cache lines.


1

This is just a single-level cache, then? That means just two possibilities when accessing: a hit or a miss, with hit rate + miss rate = 100%. It follows that the average is simply the time spent with hits and the time spent with misses, which comes out to: hit rate * hit time + miss rate * miss time


1

I think it's because when using virtual memory, you have access to disk and thus have vasts amounts of memory to store extra data structures than can help you identify each page. In cache, you don't have that much memory, so the way to do things is to add identification (tag and set) bits to each cache line so that you don't need another data structure to ...


1

First Let's define all given things L1 Cache hit: 90% & Time: 1ns L2 and RAM has hit rate 10% out of which 95% which is 9.5% in total L2 Cache hit: 9.5% & Time 20ns RAM has hit rate 5% of 10% = 0.5% RAM hit: 0.5% & Time 220ns Formula Avg Memory Access Time AMAT = L1_hit * L1_T + L2_hit * L2_T + RAM_hit * RAM_T AMAT = 0.9*1 + 9.5*20 + 0.5*...


1

Currently, cache sizes are usually so big that more than one transfer from RAM to cache is needed to completely load a cache line. But reading from RAM takes time for the RAM to receive the address of the data to be read, and then time for the actual transfer, and asking RAM to perform say four transfers in a row is much faster than accessing four random ...


1

CPUs are developed with typical code in mind. For example, indirect function calls are no problem - the destination of such a function call will be predicted, just as we do with branch prediction. Remember that "hundreds of cycles" are only "tens of nanoseconds". Typically, 3,000 cycles is just one microsecond. So if a programming pattern wastes "hundreds ...


1

The accepted answer clear most of the doubt, and here I wanna make a note here (for comp org student). We consider the addresses are not byte addressable (as mentioned in the question, they are word addresses). The equation (with +2 offset) mentioned in the textbook should not be used directly in this question. remind that offset does not need to be matched ...


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