30 votes
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What does the processor do while waiting for a main memory fetch

Memory latency is one of the fundamental problems studied in computer architecture research. Speculative Execution Speculative execution with out-of-order instruction issue is often able to find ...
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16 votes

What does the processor do while waiting for a main memory fetch

The short answer is: nothing, the processor stalls. There aren't so many possibilities. Switching to a different task isn't really an option for two reasons. That's an expensive operation, and since ...
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7 votes
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RISC machines have register renaming?

RISC machines can have register renaming, just like CISC machines can have register renaming. Register renaming is an aspect of the processor implementation, whereas RISC is an aspect of the ...
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5 votes
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what are the key advantages of pipelining

I Googled your question and found this (and this): Consider the modern way of making cars - on an assembly line. Here, there is an orderly flow of parts down a conveyor belt, and the parts are ...
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5 votes

What does the processor do while waiting for a main memory fetch

The answer to this question will vary with the architecture in question. While many CPUs will stall (ARM, x86 w/o hyperthreading, etc.) because it takes them too long to switch threads, that's not the ...
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  • 230
5 votes
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How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on ...
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  • 1,813
4 votes
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Does register renaming remove all kinds of WAR hazard?

Write-after-read (WAR) hazards are pervasive throughout all of computer systems, although different subfields call it different things. Renaming of one kind or another (and called one thing or ...
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4 votes
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Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 ... )?

Each stage of the pipeline is only as fast as the slowest stage. The calculation for the latency expresses this by taking the maximum delay (max(D1, D2, D3, D4)) ...
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  • 281
4 votes
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Clear interrupt instruction in a pipelined CPU

Such a control hazard can be handled effectively the same way that a branch misprediction is handled. Either the CLI instruction commits and the interrupt handler fetch is treated as the mispredicted ...
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3 votes
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Identifying system events affecting timing behavior of an application

You forgot the most obvious factor: the input of the program. The time taken by a program heavily depends on the input unless it does not have any input or the input comes from a small fixed set. ...
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  • 4,747
3 votes

Understanding pipeline stalls (bubbles) based on stage

A CPU pipeline has a number of stages. The exact stages vary between CPUs and some CPUs have very many stages, but obviously the first stage must be Instruction Fetch (IF) and the second stage must ...
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  • 1,000
3 votes
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Which hazards are solved by instruction reordering?

Instruction reordering in cpu-pipelines doesn't solve any hazards problem. Register renaming eliminates write-after-write data hazards on registers and write-after-read data hazards on registers. ...
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3 votes

how one memory can be accessed simultaneously in instruction fetch and data read?

Modern CPUs usually feature separate instruction and data caches, so effectively, even if from a software PoV, everything is coming from a single memory space, there are physically separate busses and ...
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  • 1,766
3 votes

CPU pipelining stages

There are many ways this kind of situation be handled. Clever compilers If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is ...
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  • 305
3 votes
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Short pipeline or long pipeline

If by pieces one means possible stages that the instruction can be split into. For example, like this "short" Classic RISC pipeline with five stages: Fetch Instruction Stage: Fetch the instruction. ...
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  • 544
3 votes
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

As an instruction must be decoded before branch prediction can occur or be deemed unneeded, That can be avoided. The fetch stage can do prediction based purely on the current PC, without looking at ...
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  • 1,813
3 votes
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How can an instruction be fetched every cycle?

So, how does the CPU fetch a new instruction every cycle, if it takes more than one cycle to even fetch an instruction? It could be done by starting the next fetch before the previous one completed. ...
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  • 1,813
2 votes

How are the control signals derived in the MIPS pipeline?

You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add. The pipelined datapath in your question is ...
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2 votes
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pipeline execution time

With a static prediction of not-taken, when the branch is not taken (correct prediction) there is no penalty. When the branch is taken ("happens"), all the instructions that were fetched after the ...
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2 votes

Pipelining and Preemption

Your question reminds me of an old joke: If the Atlantic can be crossed in 7 days with one boat, you can cross it in one day, if you have seven boats available. (there are actually many variants) ...
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  • 19.1k
2 votes
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Identical register input operands in assembly

R1 <- R0 + R0 works in every processor that permits three register operands. Nothing special needs to be done to deal with the same register driving multiple ...
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2 votes

Is there a CPU architecture which allows early register access?

Classic VLIW architectures provide this feature. Operations are statically scheduled with fixed latency and the old value would be associated with a register name until an overwriting operation ...
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2 votes

Is there a CPU architecture which allows early register access?

You are describing pipeline forwarding for data hazards. Here is a wikipedia article about it: https://en.wikipedia.org/wiki/Operand_forwarding This is a common feature of in-order processors (such ...
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  • 206
2 votes

Identifying system events affecting timing behavior of an application

I'd agree that your list includes many items that can cause execution to lengthen. But those are all directly related to the execution of the application code itself. Also consider events which ...
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2 votes

Basic question about branches and pipelines

The classic RISC pipeline resolves branches in the decode stage, which means the branch resolution recurrence is two cycles long. More information can be found in the Wikipedia article on the Classic ...
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  • 83
2 votes

Clear interrupt instruction in a pipelined CPU

External interrupt are usually processed as traps (divide by zero, MMU faults...) in pipelined CPUs, to share resources and simplify the design. They are handled late in the pipeline, which can have ...
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  • 1,766
2 votes
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In instruction pipelining, can we forward an operand more than one clock cycle?

Paul's Comment is correct: "Yes. This is one way of avoiding a structural hazard on the write ports of the register file with operations of several different latencies (i.e., having a single writeback ...
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  • 206
2 votes
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Depth of a pipeline in a CPU's architecture

I think that depth is a measure of the overlapping of instructions while number of stages is a hardware constant. When you increase the number of stages, you usually make the CPU faster but it is with ...
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2 votes
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Branch wrong prediction pipeline

It's not correct. The instruction that would determine the result of the condition is read at cycle x. The conditional branch is read at cycle x + k. k can be any value, depending on the code. For ...
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2 votes

For data-path cycles in MIPS, what determines wheter a control signal gets the "don't-care" value?

A control signal controls a single component in the architecture. When the command that is now active is not using the component this control signal controls, the control signal gets the "don't care" ...
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