7 votes
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RISC machines have register renaming?

RISC machines can have register renaming, just like CISC machines can have register renaming. Register renaming is an aspect of the processor implementation, whereas RISC is an aspect of the ...
Gilles 'SO- stop being evil''s user avatar
5 votes

Understanding pipeline stalls (bubbles) based on stage

A CPU pipeline has a number of stages. The exact stages vary between CPUs and some CPUs have very many stages, but obviously the first stage must be Instruction Fetch (IF) and the second stage must ...
Johan's user avatar
  • 1,070
5 votes
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How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on ...
harold's user avatar
  • 2,053
3 votes

Do unconditional branches cause control hazards?

YES, unconditional jumps can cause a control hazard in a pipelined machine. we know with 100% certainly that B will be executed since an unconditional jump instruction A preceded it. Well, we know,...
Ran G.'s user avatar
  • 20.7k
3 votes

how one memory can be accessed simultaneously in instruction fetch and data read?

Modern CPUs usually feature separate instruction and data caches, so effectively, even if from a software PoV, everything is coming from a single memory space, there are physically separate busses and ...
Grabul's user avatar
  • 1,860
3 votes
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Identifying system events affecting timing behavior of an application

You forgot the most obvious factor: the input of the program. The time taken by a program heavily depends on the input unless it does not have any input or the input comes from a small fixed set. ...
Sarvottamananda's user avatar
3 votes

CPU pipelining stages

There are many ways this kind of situation be handled. Clever compilers If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is ...
Isu's user avatar
  • 325
3 votes
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Short pipeline or long pipeline

If by pieces one means possible stages that the instruction can be split into. For example, like this "short" Classic RISC pipeline with five stages: Fetch Instruction Stage: Fetch the instruction. ...
Klorax's user avatar
  • 544
3 votes
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?

As an instruction must be decoded before branch prediction can occur or be deemed unneeded, That can be avoided. The fetch stage can do prediction based purely on the current PC, without looking at ...
harold's user avatar
  • 2,053
3 votes
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How can an instruction be fetched every cycle?

So, how does the CPU fetch a new instruction every cycle, if it takes more than one cycle to even fetch an instruction? It could be done by starting the next fetch before the previous one completed. ...
harold's user avatar
  • 2,053
2 votes

Identifying system events affecting timing behavior of an application

I'd agree that your list includes many items that can cause execution to lengthen. But those are all directly related to the execution of the application code itself. Also consider events which ...
Brian Hibbert's user avatar
2 votes

How are the control signals derived in the MIPS pipeline?

You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add. The pipelined datapath in your question is ...
Ran G.'s user avatar
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2 votes
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In instruction pipelining, can we forward an operand more than one clock cycle?

Paul's Comment is correct: "Yes. This is one way of avoiding a structural hazard on the write ports of the register file with operations of several different latencies (i.e., having a single writeback ...
nic's user avatar
  • 206
2 votes
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Depth of a pipeline in a CPU's architecture

I think that depth is a measure of the overlapping of instructions while number of stages is a hardware constant. When you increase the number of stages, you usually make the CPU faster but it is with ...
Niklas Rosencrantz's user avatar
2 votes
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What's the difference between dynamic and static pipelines?

The reference I've mentioned is actually self-contained; i.e, the answer I was looking for was there all the time. But considering that others could have the same doubt, I will reproduce an snippet ...
Humberto Fioravante Ferro's user avatar
2 votes

which Pipelining architecture, should i use and how to distinguish them!

In computer architecture, there is absolutely nothing that you must do. There are always compromises, everything has advantages and disadvantages, and advantages and disadvantages change over time. ...
gnasher729's user avatar
2 votes

Can an instruction with a dependency read the register in same cycle as it's being written?

With modern processors, arithmetic units tend to be able to deliver results simultaneously to a register, and to another arithmetic unit that requires that result. There is a limit to this, so if ...
gnasher729's user avatar
2 votes
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Branch wrong prediction pipeline

It's not correct. The instruction that would determine the result of the condition is read at cycle x. The conditional branch is read at cycle x + k. k can be any value, depending on the code. For ...
gnasher729's user avatar
2 votes

For data-path cycles in MIPS, what determines wheter a control signal gets the "don't-care" value?

A control signal controls a single component in the architecture. When the command that is now active is not using the component this control signal controls, the control signal gets the "don't care" ...
A. Steiner's user avatar
2 votes
Accepted

Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?

You are right that the clock speed is determined by the slowest stage. But on most architectures, it is not true that fetching (or any kind of memory access) takes one cycle. This is an illusion ...
Amaury Pouly's user avatar
  • 1,181
2 votes

Is there a CPU architecture which allows early register access?

You are describing pipeline forwarding for data hazards. Here is a wikipedia article about it: https://en.wikipedia.org/wiki/Operand_forwarding This is a common feature of in-order processors (such ...
nic's user avatar
  • 206
2 votes

Basic question about branches and pipelines

The classic RISC pipeline resolves branches in the decode stage, which means the branch resolution recurrence is two cycles long. More information can be found in the Wikipedia article on the Classic ...
bopia's user avatar
  • 83
2 votes

Bubble in a pipeline

Inserting NOPs is the stall. It delays execution until the result is ready. A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to ...
ratchet freak's user avatar
2 votes

Difference between delayed branches and out-of-order execution

I suppose you could view branch delay slots as a very special sort of out-of-order execution, but this isn't usually what we mean when we talk about out-of-order execution: generally, we're referring ...
D.W.'s user avatar
  • 159k
2 votes

Difference between delayed branches and out-of-order execution

The "normal" way to execute code goes like this: There is a program counter (PC). The processor executes the instruction pointed to by the program counter. If that instruction is an unconditional ...
gnasher729's user avatar
2 votes

Branch Prediction question

I figured out what he means: fetch the instruction and decode it, but do not fetch the next instruction until you've determined whether it's a branch or non-branch instruction. For the non-branch ...
supmethods's user avatar
2 votes

From where does the Fetch Unit get its instructions?

The instructions come from some part of memory, pointed to by the Program Counter (PC) aka Instruction Pointer (IP). In modern computers, instructions tend to share the same RAM used for everything ...
Draconis's user avatar
  • 7,138
2 votes
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Case where anti-dependency doesn't need pipeline stalling

You can eliminate anti-dependences (WAR dependences) with register renaming, so if you're doing renaming there will be no stalls from anti-dependences. The other case is if you already know the write ...
Wandering Logic's user avatar
2 votes

Why cannot Operand forwarding remove all RAW hazards?

Sure! And I can assure that is a fairly good question, if you are not able to see all the combinations. See, operand forwarding can indeed remove all RAW hazards inside CPU but it is helpless when not ...
Bhartendu Kumar's user avatar

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