7
votes
Accepted
RISC machines have register renaming?
RISC machines can have register renaming, just like CISC machines can have register renaming. Register renaming is an aspect of the processor implementation, whereas RISC is an aspect of the ...
5
votes
Accepted
what are the key advantages of pipelining
I Googled your question and found this (and this):
Consider the modern way of making cars - on an assembly line. Here, there is an orderly flow of parts down a conveyor belt, and the parts are ...
- 76
5
votes
Accepted
How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?
Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on ...
- 1,923
4
votes
Understanding pipeline stalls (bubbles) based on stage
A CPU pipeline has a number of stages.
The exact stages vary between CPUs and some CPUs have very many stages, but obviously the first stage must be Instruction Fetch (IF) and the second stage must ...
- 1,030
4
votes
Accepted
Clear interrupt instruction in a pipelined CPU
Such a control hazard can be handled effectively the same way that a branch misprediction is handled. Either the CLI instruction commits and the interrupt handler fetch is treated as the mispredicted ...
- 2,988
3
votes
how one memory can be accessed simultaneously in instruction fetch and data read?
Modern CPUs usually feature separate instruction and data caches, so effectively, even if from a software PoV, everything is coming from a single memory space, there are physically separate busses and ...
- 1,786
3
votes
Accepted
Identifying system events affecting timing behavior of an application
You forgot the most obvious factor: the input of the program. The time taken by a program heavily depends on the input unless it does not have any input or the input comes from a small fixed set.
...
- 4,787
3
votes
Do unconditional branches cause control hazards?
YES, unconditional jumps can cause a control hazard in a pipelined machine.
we know with 100% certainly that B will be executed since an unconditional jump instruction A preceded it.
Well, we know,...
- 20.5k
3
votes
CPU pipelining stages
There are many ways this kind of situation be handled.
Clever compilers
If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is ...
- 325
3
votes
Accepted
Short pipeline or long pipeline
If by pieces one means possible stages that the instruction can be split into. For example, like this "short" Classic RISC pipeline with five stages:
Fetch Instruction Stage: Fetch the instruction.
...
- 544
3
votes
Accepted
How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?
As an instruction must be decoded before branch prediction can occur or be deemed unneeded,
That can be avoided. The fetch stage can do prediction based purely on the current PC, without looking at ...
- 1,923
3
votes
Accepted
How can an instruction be fetched every cycle?
So, how does the CPU fetch a new instruction every cycle, if it takes more than one cycle to even fetch an instruction?
It could be done by starting the next fetch before the previous one completed.
...
- 1,923
2
votes
Accepted
pipeline execution time
With a static prediction of not-taken, when the branch is not taken (correct prediction) there is no penalty. When the branch is taken ("happens"), all the instructions that were fetched after the ...
- 2,988
2
votes
Pipelining and Preemption
Your question reminds me of an old joke:
If the Atlantic can be crossed in 7 days with one boat, you can cross it in
one day, if you have seven boats available. (there are actually many variants)
...
- 19.2k
2
votes
How are the control signals derived in the MIPS pipeline?
You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add.
The pipelined datapath in your question is ...
- 20.5k
2
votes
Is there a CPU architecture which allows early register access?
Classic VLIW architectures provide this feature. Operations are statically scheduled with fixed latency and the old value would be associated with a register name until an overwriting operation ...
- 2,988
2
votes
Is there a CPU architecture which allows early register access?
You are describing pipeline forwarding for data hazards. Here is a wikipedia article about it:
https://en.wikipedia.org/wiki/Operand_forwarding
This is a common feature of in-order processors (such ...
- 206
2
votes
Identifying system events affecting timing behavior of an application
I'd agree that your list includes many items that can cause execution to lengthen. But those are all directly related to the execution of the application code itself.
Also consider events which ...
- 751
2
votes
Accepted
In instruction pipelining, can we forward an operand more than one clock cycle?
Paul's Comment is correct:
"Yes. This is one way of avoiding a structural hazard on the write ports of the register file with operations of several different latencies (i.e., having a single writeback ...
- 206
2
votes
Accepted
Depth of a pipeline in a CPU's architecture
I think that depth is a measure of the overlapping of instructions while number of stages is a hardware constant. When you increase the number of stages, you usually make the CPU faster but it is with ...
2
votes
which Pipelining architecture, should i use and how to distinguish them!
In computer architecture, there is absolutely nothing that you must do. There are always compromises, everything has advantages and disadvantages, and advantages and disadvantages change over time.
...
- 27.1k
2
votes
Can an instruction with a dependency read the register in same cycle as it's being written?
With modern processors, arithmetic units tend to be able to deliver results simultaneously to a register, and to another arithmetic unit that requires that result.
There is a limit to this, so if ...
- 27.1k
2
votes
Accepted
Branch wrong prediction pipeline
It's not correct. The instruction that would determine the result of the condition is read at cycle x. The conditional branch is read at cycle x + k. k can be any value, depending on the code. For ...
- 27.1k
2
votes
For data-path cycles in MIPS, what determines wheter a control signal gets the "don't-care" value?
A control signal controls a single component in the architecture. When the command that is now active is not using the component this control signal controls, the control signal gets the "don't care" ...
- 21
2
votes
Basic question about branches and pipelines
The classic RISC pipeline resolves branches in the decode stage, which means the branch resolution recurrence is two cycles long. More information can be found in the Wikipedia article on the Classic ...
- 83
2
votes
Clear interrupt instruction in a pipelined CPU
External interrupt are usually processed as traps (divide by zero, MMU faults...) in pipelined CPUs, to share resources and simplify the design.
They are handled late in the pipeline, which can have ...
- 1,786
2
votes
Accepted
Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?
You are right that the clock speed is determined by the slowest stage. But on most architectures it is not true that fetching(or any kind of memory access in fact) takes one cycle. This is an illusion ...
- 1,171
2
votes
Bubble in a pipeline
Inserting NOPs is the stall. It delays execution until the result is ready.
A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to ...
- 4,228
2
votes
Difference between delayed branches and out-of-order execution
I suppose you could view branch delay slots as a very special sort of out-of-order execution, but this isn't usually what we mean when we talk about out-of-order execution: generally, we're referring ...
D.W.♦
- 150k
2
votes
Difference between delayed branches and out-of-order execution
The "normal" way to execute code goes like this: There is a program counter (PC). The processor executes the instruction pointed to by the program counter. If that instruction is an unconditional ...
- 27.1k
Only top scored, non community-wiki answers of a minimum length are eligible