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Memory latency is one of the fundamental problems studied in computer architecture research. Speculative Execution Speculative execution with out-of-order instruction issue is often able to find useful work to do to fill the latency during an L1 cache hit, but usually runs out of useful work after 10 or 20 cycles or so. There have been several attempts to ...

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The short answer is: nothing, the processor stalls. There aren't so many possibilities. Switching to a different task isn't really an option for two reasons. That's an expensive operation, and since the current task and other task are competing for space in the cache, switching to the other task may itself require a main memory access, and so may switching ...

6

In a classic 5-stage RISC pipeline, WB writes a value into a register. If the instruction doesn't write a value into a register (e.g. store), then that stage isn't used. I1 stores a result into a register (namely R1), so it uses WB. I2 stores a result into a register (R1) so it uses WB. I3 does not store a result into a register, so it doesn't use WB. ...

6

In a scalar implementation, a structural hazard can exist if specific execution hardware is not fully pipelined. For some operations (e.g., multiplication and especially division) the cost of implementing full pipelining may not be considered worthwhile for the expected frequency of the operation. In a superscalar implementation, a structural hazard may ...

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I don't know which case is prevalent, but I would like to offer some thoughts on your proposal of double pipelines. First of all, you would need double the wire which would consume double the energy and produce double the heat while active. While not needed, on the other hand, it would be completely useless. So one could argue that it is not a good use of ...

6

RISC machines can have register renaming, just like CISC machines can have register renaming. Register renaming is an aspect of the processor implementation, whereas RISC is an aspect of the instruction set, so they are fairly orthogonal: there can be two processors implementing the same architecture (i.e. accepting the same code), but in different ways (and ...

5

The answer to this question will vary with the architecture in question. While many CPUs will stall (ARM, x86 w/o hyperthreading, etc.) because it takes them too long to switch threads, that's not the approach taken by every architecture. In some architectures, each thread scheduled on a CPU has its own independent register file, so the processor may simply ...

5

I Googled your question and found this (and this): Consider the modern way of making cars - on an assembly line. Here, there is an orderly flow of parts down a conveyor belt, and the parts are processed by different stations (also called segments of the assembly line). Each segment does one thing, over and over. The segments are coordinated to exploit the ...

4

The first instruction (I1) will pass through all the stages one by one without any stall and will take $3+4+2+4=13$ cycles. The second instruction (I2) goes next and it begins at the end of cycle 3. As soon as it finishes the execution of S1, it is ready to go to next stage. But it is occupied by the previous instruction. Hence, I2 needs to stall for 1 ...

4

Each stage of the pipeline is only as fast as the slowest stage. The calculation for the latency expresses this by taking the maximum delay (max(D1, D2, D3, D4)) and multiplying it by N, which is the number of stages. Thus: N*max(D1, D2, D3, D4). Keep in mind, N is the number of stages, not instructions. The formula measures the latency, not the total run ...

4

Such a control hazard can be handled effectively the same way that a branch misprediction is handled. Either the CLI instruction commits and the interrupt handler fetch is treated as the mispredicted path and fetch is restarted after the CLI or the CLI instruction is not committed and the interrupt handler is treated as the correct path.

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Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on just the value from the register, in parallel with adding the offset to it. Usually the small offset won't change the page being accessed, if that works out then ...

3

You forgot the most obvious factor: the input of the program. The time taken by a program heavily depends on the input unless it does not have any input or the input comes from a small fixed set. Other factors can be classified into two classes: 1) Internal factors and 2) External factors. Internal factors: 1) Input 2) Waiting for I/O 3) Waiting for ...

3

Write-after-read (WAR) hazards are pervasive throughout all of computer systems, although different subfields call it different things. Renaming of one kind or another (and called one thing or another) is the most general method I can think of for working around these kinds of problems. Register renaming is the form of renaming used in CPUs that want to ...

3

Instruction reordering in cpu-pipelines doesn't solve any hazards problem. Register renaming eliminates write-after-write data hazards on registers and write-after-read data hazards on registers. Speculative execution tries to find some useful work to do in the presence of control hazards. Instruction reordering only works between instructions that are ...

3

A CPU pipeline has a number of stages. The exact stages vary between CPUs and some CPUs have very many stages, but obviously the first stage must be Instruction Fetch (IF) and the second stage must be Instruction decode (ID). If an instruction is not in the cache it cannot be fetched and delays occur. Let's call our missing instruction $A$. The only way ...

3

Instruction Decode and Register Read are done in parallel on that stage in order to prevent needing to wait on either to complete. There's no reason not to do this since they are both known at that point in time for the MIPS-Pipeline, and since they will most likely be needed for the next step (Execution Cycle). By "no reason", I mean that you would ...

3

Modern CPUs usually feature separate instruction and data caches, so effectively, even if from a software PoV, everything is coming from a single memory space, there are physically separate busses and memories for instructions and data ("harvard", which is used for all reasonably fast CPUs nowadays). There are also multi-port memories able to sustain ...

3

There are many ways this kind of situation be handled. Clever compilers If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is reading from the memory location 0x12345 and the variable allocated at memory location 0x12345 is not "volatile", compiler will optimize your code so that the next ...

2

You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add. The pipelined datapath in your question is based on a single-cycle MIPS that doesn't support jumps (Figure 5.21 in Patterson and Hennessy). In order to add jump support, consider the single-cycle MIPS datapath of Figure 5.24; then add the ...

2

In one sense, the effect of branch prediction is more critical in the fetching of instructions since an instruction which is not fetched cannot be executed. With respect to executing both paths of a branch, this is called eager execution and has been researched somewhat substantially. Augustus K. Uht and Vijay Sindagi's "Disjoint Eager Execution: An ...

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Here is an analogy from the world of light bulbs. An incandescent light bulb operates at 15LPW (Lumens per Watt), while a LED light bulb operates at 45LPW. Suppose for the moment that both give the same spectrum of light (which is wrong). Suppose we feed the incandescent light bulb 9 Watts and the LED light bulb 3 Watts. Both will produce 105 Lumens, but the ...

2

What you describe (split job into parts, total CPU usage stays the same) indicates that your task is (or gets) I/O (or perhaps RAM) bound. Try splitting among several machines, not just several processes on the same machine. If the program you are using comes from somewhere else, see if there are newer versions, bug reports on performance, or perhaps tricks ...

2

The peak possible frequency is, no doubt, equal to the inverse of maximum time supported by each stage. The stage consuming maximum time is the limiting condition and your anwer is correct.

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R1 <- R0 + R0 works in every processor that permits three register operands. Nothing special needs to be done to deal with the same register driving multiple read ports. Each register-file read port is just a multiplexer. If you have $N$ registers driving the $N$ inputs of one $N$-to-$1$ multiplexer and the same $N$ registers driving the $N$ inputs of ...

2

External interrupt are usually processed as traps (divide by zero, MMU faults...) in pipelined CPUs, to share resources and simplify the design. They are handled late in the pipeline, which can have some negative effects on interrupt latency. For traps, the pipeline is flushed, all the partially executed instructions are discarded. When implementing the ...

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With a static prediction of not-taken, when the branch is not taken (correct prediction) there is no penalty. When the branch is taken ("happens"), all the instructions that were fetched after the branch instruction are flushed from the pipeline (except for any branch delay slot instructions) when the branch instruction is evaluated. Instruction fetch ...

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Your question reminds me of an old joke: If the Atlantic can be crossed in 7 days with one boat, you can cross it in one day, if you have seven boats available. (there are actually many variants) Your problem is the problem of assembly lines in general, and that is the technical model of a pipelined processor. On the assembly line for making car (I am of ...

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I'd agree that your list includes many items that can cause execution to lengthen. But those are all directly related to the execution of the application code itself. Also consider events which have nothing directly to do with the application itself such as: Context Switching: IF another process is allowed to preempt your application, there is a cost to ...

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You are describing pipeline forwarding for data hazards. Here is a wikipedia article about it: https://en.wikipedia.org/wiki/Operand_forwarding This is a common feature of in-order processors (such as MIPS32). Since they are not operating out-of-order, the data hazard detection logic detects that the result will not be available during the clock cycle ...

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