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104

Addition is fast because CPU designers have put in the circuitry needed to make it fast. It does take significantly more gates than bitwise operations, but it is frequent enough that CPU designers have judged it to be worth it. See https://en.wikipedia.org/wiki/Adder_(electronics). Both can be made fast enough to execute within a single CPU cycle. They'...


58

The question is: under what constraints? There are certainly problems where, if we ask the question "can we solve this problem on hardware X in the given amount of time", the answer will be no. But this is not a "future-proof" answer: things which in the past could not be done fast enough in a single core probably can be now, and we can't predict what ...


47

If you don't care about the running time, anything you can do on a multi-core machine, you can do on a single-core machine. A multi-core machine is just a way of speeding up some kinds of computations. If you can solve a problem in time $T$ on a multi-core machine with $n$ cores, then you can solve it time $\sim Tn$ (or less look at Amdahl's law) on a ...


39

The best answer I can give is, it doesn't really "look" like anything. The instruction currently being executed by the CPU is represented by a series of wires, some of which have a high voltage, some of which have a low voltage. You can interpret the high and low voltages as zeroes and ones, but you can equally well interpret groups of high and low voltages ...


38

There are several aspects. The relative cost of a bitwise operation and an addition. A naive adder will have a gate-depth which depend linearly of the width of the word. There are alternative approaches, more costly in terms of gates, which reduce the depth (IIRC the depth then depend logarithmically of the width of the word). Others have given ...


24

CPUs operate in cycles. At each cycle, something happens. Usually, an instruction takes more cycles to execute, but multiple instructions are executed at the same time, in different states. For example, a simple processor might have 3 steps for each instruction: fetch, execute and store. At any time, 3 instructions are being processed: one is being fetched, ...


20

None of the above. As you noted, DMA and demand paging can be useful features but are not necessary to support multiple users and multiprocessing. Address translation is not necessary even for memory protection. Memory protection can be separated from address translation via a protection lookaside buffer or memory protection unit. Providing a distinct ...


17

As other answers have pointed out, a single CPU can always emulate multiple CPUs by slicing time and playing the role of each virtual CPU. This emulation will certainly calculate the correct answers. In the real world, execution time may be important. It could mean the difference between a mediocre frame rate and a stellar visual experience. Or the ...


12

Processors are clocked, so even if some instructions can clearly be done faster than others, they may well take the same number of cycles. You'll probably find that the circuitry required to transport data between registers and execution units is significantly more complicated than the adders. Note that the simple MOV (register to register) instruction ...


12

Addition is important enough to not have it wait for a carry bit to ripple through a 64-bit accumulator: the term for that is a carry-lookahead adder and they are basically part of 8-bit CPUs (and their ALUs) and upwards. Indeed, modern processors tend to need not much more execution time for a full multiplication either: carry-lookahead is actually a ...


11

"Look like" implies a metaphor. If we take "what will it look like" literally, it's going to look like a fancy etched piece of silicon sitting on its motherboard. Clearly metaphor was the goal. To build the metaphor, we need to look at what it really is first. Then we can build a metaphor that is acceptable. This is a bit long, but fortunately, it ends ...


10

The instructions set architecture (ISA) is the contract between the hardware designer and the software designer. Anything that changes the contract, changes the ISA. The question you have to answer is: given every possible program written with this particular ISA, do any of them have different behavior (give a different answer) if we remove the branch ...


10

Check out this video, in particular 1:00 to 1:17. That's exactly what it looks like when a program is running on a computer. The two rows of lights show the current contents of the address register and the data register. The PDP-11 doesn't have an instruction register, but if there were one and there were lights on the front to show its contents, it would ...


9

I think you'd be hard pressed to find a processor that had addition taking more cycles than a bitwise operation. Partly because most processors must carry out at least one addition per instruction cycle simply to increment the program counter. Mere bitwise operations aren't all that useful. (Instruction cycle, not clock cycle - e.g. the 6502 takes a minimum ...


9

Optimization is not really something that should be guessed at. Instead you need to measure what is going on to determine the chokepoints and where changes need to be made. A faster processor may have little or no effect especially since the CPU utilization is not maxed out. CPU speed affects only those parts of the program which are actually running on the ...


8

I remember a counter-example from the 1980s: OS-9/68000 was quite popular then: a multi-user, multi-processing real-time operating system for the Motorola 68K processor family, loosely patterned after UNIX. It didn't require any of the features from your list. The 68000 didn't have address translation. OS-9 compilers produced position-independent code that ...


8

The exact details of when (or even how) to increment the program counter are implementation specific details. There are however a few considerations that come into play across most computers. After sending out the PC address, there is (almost) always a delay waiting for memory to respond. Thus there's often not a lot going on. One possible use of this "dead"...


8

At the gate level, you are correct that it takes more work to do addition, and thus takes longer. However, that cost is sufficiently trivial that doesn't matter. Modern processors are clocked. You cannot do instructions at anything except multiples of this clock rate. If the clock rates were pushed higher, to maximize the speed of the bitwise operations, ...


8

Since the CPU works in fixed clock cycles, nothing is really continuous, only seems so because the discretization is sensitive enough. Suppose your CPU clock rate is $1\text{GHz}=10^9Hz$. If the CPU only devotes one in $t$ clock cycles to processing audio (and utilizes the remaining clock cycles for unrelated tasks) then you have a delay of $\approx t\cdot ...


7

You can try taking a simple program and compiling it to native machine code. (Java normally compiles to JVM code, but Andrew Tennenbaum has a book where he describes how to design a CPU that runs that natively, so it will do.) On GCC, for example, you give the compiler the -S switch. This will tell you that anything tricky, like I/O, is implemented by ...


7

In circumstances 1 and 4, the current process can't continue running. Therefore, there's no choice: the OS scheduler has to step in and select a different process. In circumstances 2 and 3, the OS scheduler has a choice: it can either allow the current process to continue running, or it could step in and put the current process to sleep and select a ...


7

No. The Operating System is going to use context switching and virtual memory to hide the fact that there are multiple processes running on the computer. Native code does not mean you have full control to the CPU registers, global physical memory. Your program, if not privileged, is still running in user mode. You need to use syscalls to do lower level tasks....


7

It's much harder to develop really nefarious data races with a single CPU. I mean, sure, you can pull off tearing between words if you interrupt a single CPU, but can you build exotic scenarios where there is no single interleaving of threads which does what you want? Okay, maybe making insidious bugs doesn't count as a valid use of multi-code advancements....


7

Modern processors are clocked: Every operation takes some integral number of clock cycles. The designers of the processor determine the length of a clock cycle. There are two considerations there: One, the speed of the hardware, for example measured as the delay of a single NAND-gate. This depends on the technology used, and on tradeoffs like speed vs. power ...


7

40 years ago, you might have had a computer where the CPU controlled the speaker directly. Those times are over, long ago. You may have a computer with a primitive sound card. Such a sound card will have a buffer for stereo audio samples, that buffer can be filled, the output function will be started, and the sound card starts generating audio from the ...


7

TL;DR: No. It depends on the OS and the keyboard. I'll show you how to determine this yourself on a Linux machine. I'm using Ubuntu 16.04 on an x86 processor. So if you are using a fairly modern version of Linux and an x86 processor, then the steps will be pretty much the same. I have a USB keyboard (and mouse) and almost everyone else does. Open a new ...


6

If you need to observe a process running on a single processing element without disturbing its real-time behavior (or as little as possible), like for benchmarking or activity logging, you'll probably need a separate processing resource.


6

1. (A summary of the answer-in-comments by Jukka) Startup code is stored in ROM (non-volatile memory) at a fixed address X. When you activate the "reset" signal in the CPU, the CPU will initialise its registers to certain hard-coded values. The instruction pointer is one of these registers that are initialised to certain hard-coded values. In essence, the ...


6

Let me correct a few things that were not mentioned that explicitely in your existing answers: I know that bitwise operations are so fast on modern processors, because they can operate on 32 or 64 bits on parallel, This is true. Labeling a CPU as "XX" bit usually (not always) means that most of its common structures (register widths, addressable RAM etc....


6

The hardware designers implementing and testing (and testing and testing) the processor actually do use visual models to see what their designs are doing. Most (if not all) HDL simulation tools output wave views of all of the registers and wires to allow for easy debugging. The screenshot below (taken from here) shows these waves from the VCS simulator for a ...


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