# Tag Info

40

Your suspicion is correct. The CPU doesn't care about the semantics of your data. Sometimes, though, it does make a difference. For example, some arithmetic operations produce different results when the arguments are semantically signed or unsigned. In that case you need to tell the CPU which interpretation you intended. It is up to the programmer to make ...

31

I'd suggest you look into the wonderful world of Compiler Construction! The answer is that it's a bit of a complicated process. To try to give you an intuition, remember that variable names are purely there for the programmer's sake. The computer will ultimately turn everything into addresses at the end. Local variables are (generally) stored on the stack: ...

26

The trick to making this work is "paging." When bringing data from a hard disk into physical memory, you don't just bring a few bytes. You bring an entire page. 4k bytes is a very common page size. If you only need to keep track of pages, not each individual byte, the mapping becomes much cheaper. If you have a 48 bit address space and 4096 byte pages, ...

24

When a computer stores a variable, when a program needs to get the variable's value, how does the computer know where to look in memory for that variable's value? The program tells it. Computers do not natively have a concept of "variables" - that's entirely a high-level language thing! Here's a C program: int main(void) { int a = 1; return a + 3; ...

14

As others have already answered, today's common CPUs do not know what a given memory position contains; the software decides. However, there are other possibilities. Lisp Machines for example used a tagged architecture which stored the type of each memory position; that way the hardware itself could do some of the work of high-level languages. And even now,...

10

Oblivious RAM is an interface between a program and the physical RAM that when you perform a read or write, does both at the same time on the physical RAM to hide if you are reading or writing. Plus, it shuffles the memory from time to time so that an adversary seeing only accesses to the physical RAM cannot know whetever you accessed the same data twice or ...

9

From a computer architecture point of view, and with the caveat that nomenclature sometimes varies, especially when there is a family of related architectures which has evolved for a long time, or when the marketing department decides to that the usual terms have to used in another way (either to put the product in better light by using a bigger number, or ...

9

Bytes are transferred from memory to disk using an I/O protocol (e.g. SCSI) that specifies the bit order of transmission in the case of a serial protocol, or for parallel protocols specifies which pin upon which each bit in a byte should be transmitted. For bytes moved from memory over the network, the network link level protocol (e.g. Ethernet) specifies ...

8

I am not sure if this is actually on-topic here, but anyway. The main memory in x86 architectures is addressed byte-wise. If you want to retrieve 16 bits from address 2000h (note that AX is a 16 register), then you will need to read 8 bits from 2000h and 8 bits from 2001h. This is why the operation needs to read "2 cells". Note that the term "cell" is not ...

8

Network latency is orders of magnitude too high for a remote server to usefully share its RAM directly, even if you could cobble together a virtualization layer to make it work. However, today's network speeds are high enough that remote RAM based key/value stores like memcached can compete favorably with hammering a local database due to insufficient local ...

8

Your assumption that the variable is sent to the CPU is wrong. Every program must be compiled to some machine code (or it will be interpreted, but it roughly comes down to the same thing). The idea of compilation is to translate the human-readable code to a series of bits, which can then be read by the processor. In order to get an idea of what those series ...

7

Usermode to kernelmode: Wrong! ;-) Yes, interrupts are processed in kernel mode, and originally the way to enter kernel mode was by an interrupt forced somehow by software. On the DEC 2020 there was a set of UIOs (Unimplemented Instruction Opcodes), calling any of those caused a trap to the operating system. They included floating point instructions (if not ...

7

Wikipedia has great information on this topic, but as a brief, simplified explanation, know that it boils down mainly to the involvement of mechanical moving parts in a traditional Hard Disk Drive (HDD). The size of the addressing space in itself doesn't affect the access times. Otherwise you could theoretically build a very small hard-disk drive with only ...

6

Your sources are probably referring to the fact that, as a high-level programmer, you usually can't access the machine representation of bits in a byte. Even when you perform bitwise operations (like bitwise and or shift) you're manipulating standard binary representations of bytes, not necessarily the bit representation of bytes in your computer. See https:...

6

The DMA engine doesn't grab the bus for the duration of the whole transfer, only while specific data is being transferred. Yes, that means CPU acces to memory is hampered, but not shut off completely. The CPU can also work with data from its cache in the meantime.

6

I guess you got the access time wrong. Access time means time to locate a data on a memory. So, whoever accesses the memory (be it CPU or some other device) it will be the same. Coming to first question here. A block is transferred from L2 to L1. And L1 block size being 4 words and data bandwidth being 4 bytes, it requires 1 L2 access (for read) and 1 L1 ...

6

For a memory read to be relevant to the algorithm, the information read in must be processed in some way. If the information is never compared or used as input to any operator, it will not affect the algorithm and thus was unnecessary to read in the first place. If there were an operator that could accept a variable number of inputs, a number that could grow ...

5

The operating system (with help from the CPU) keeps a page table, which is a mapping of each virtual page for to the physical page it is mapped to. The page table also includes a bit for whether a particular page is currently mapped. For every load and store instruction the hardware walks the page table (or at least a cached portion of it.) If the virtual ...

5

A faulting prefetch is one which (as gnasher729's answer notes) generates any translation (e.g., invalid page table entry), permission, or other fault (e.g., ECC failure, data watchpoint match) associated with the access. Such a prefetch acts as if the memory location was accessed normally. For data accesses such a prefetch can be provided by software on ...

5

Some machine instruction sets include instructions for which 'small' constants are part of the instruction, either explicitly or implicitly. E.g the set of 'add' instructions can include 'add immediate', where the value to be added fills out the rest of the instruction bits. In that case, the operation does not need to fetch the constant value from a ...

5

If you want to use lookup tables, and you have 4GB of memory, you'll only be able to use a lookup table with about $2^{32}$ entries or fewer, so you'll only be able to handle multiplication of numbers that are at most 16 bits long. If you want to multiply larger numbers, you won't be able to use lookup tables for multiplication. Typically we want to ...

5

Computer hardware is fundamentally parallel. Even a modern single CPU core is pipelined, meaning that at the same instant in time, one physical part of the CPU is initiating a fetch of an instruction, another is decoding a slightly earlier fetched instruction, another is calculating the new result of a slightly earlier decoded instruction, and another is ...

4

The calculation is in bytes since the memory is addressed in units of bytes. If a machine word is $N$ bits and an addressed is stored in a register whose size is a single machine word, then you can address $2^N$ different locations, each of which is a byte (in principle, that could depend on the CPU, but I'm not aware of any CPU which addresses its memory in ...

4

Deleting is not necessarily destroying data. It can be done (much faster, indeed) by making it inaccessible. You can do it by erasing critical information from the data structures that are used to index the data you want to delete. How exactly this is done depends on how the storage device is organized (formatted).

4

First there is the answer already given by André Souza Lemos. The data need not be destroyed. It is usually sufficient to mark the corresponding space as unused in some table, so that the system will no longer try to read it: it considers that there is nothing stored there. But the data is often still there, often fairly easy to find, even when some key ...

4

Yes. The program just gets a byte from the memory and it can interpret it however it wants.

4

It's unclear what you mean. A prefetch is faulting exactly when the actual access to the same data would be faulting. On the other hand, hardware that allows pre-fetches might not actually implement the faults, but only fault if there is an actual access. This is very useful if the official semantics of the prefetch is "no operation", allowing prefetches ...

4

The way you access the array affects performance. It depends on how the matrix is represented and stored in memory. Often a matrix is stored in row-major order, so that consecutive elements of a row are contiguous in memory. Reading memory in contiguous locations is faster than jumping around among locations. As a result, if the matrix is stored in row-...

4

People don't usually refer to the hard drive as "memory" though the term "external memory" is common in this area of the literature. As far as disk accesses are concerned, they are taken into account in the analysis of algorithms that are explicitly written to access disk. Some of the more popular models are the two-level external memory model, the parallel ...

4

You have it backwards. $t_m$ is what's growing exponentially relative to $t_c$. Or rather, $t_c$ is decreasing exponentially at a rate faster than $t_m$. $t_c$ and $t_m$ are the times the accesses take which gets smaller as the speeds improve. So, as the paper states, eventually memory performance, i.e. $t_m$ comes to dominate. The "wall" is the point ...

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