Skip to main content
3 votes
Accepted

RAM architecture vs. CPU architecture

Computers have had a number of different ways of managing mismatches between bit count and memory size over the years. The general theme is that "pure" n-bit CPUs are rare. Instead, CPUs ...
Mark's user avatar
  • 995
2 votes

How many bits do the pointers take?

They say “pointer” but use that word in a very nonstandard way. What they actually mean is array indexes. Every item has an index from 0 to n-1. If n < 2^k then you need only k bits to store such ...
gnasher729's user avatar
  • 30.5k
1 vote

Byte addressing and alignment

Let’s say you have an old CPU with 4 byte registers and 4 byte memory bus. Reading from memory must be aligned, so you can read bytes 100-103, 104-107 etc for example. If your processor wants bytes ...
gnasher729's user avatar
  • 30.5k
1 vote

Same Address and Write signal for two block of RAM?

You do write data in second block whenever you write data in 1st block of memory. You can provide independent Data In to each block and expect it to be readable independently at the Data Outs: the ...
greybeard's user avatar
  • 1,074
1 vote

If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?

Cort Ammon's answer says multi-level page tables [let] us be a bit more efficient, keeping pages only for regions of the address space that we are actually using. and gnasher729's answer says 1 GB ...
benrg's user avatar
  • 2,157

Only top scored, non community-wiki answers of a minimum length are eligible