80
"Back in the day" computers were defined more by their word size, for example the PDP-8 had 12-bit words composed of two 6-bit "bytes". A "nibble" was half a byte, or 3 bits in this case (and here the op codes were 3 bits).
It is only in recent decades that 8-bit bytes became so prevalent as to make them the default.
Calling the NES 8-bit is less ambiguous ...
44
A) Historically, machines have been characterized by number of bits per 'machine word'. Why should NES be handled differently?
B) Calling it a 'byte' is not as clear since historically a 'byte' has not always been composed of eight bits (e.g some early machines had six bits per byte). Admittedly this is not so strong a point anymore.
C) On a side note: I ...
41
Your suspicion is correct. The CPU doesn't care about the semantics of your data. Sometimes, though, it does make a difference. For example, some arithmetic operations produce different results when the arguments are semantically signed or unsigned. In that case you need to tell the CPU which interpretation you intended.
It is up to the programmer to make ...
25
Sure. In principle, given appropriate hardware, you could have just a disk, with everything stored on disk. Any time the CPU did a load or store instruction, there could be some hardware that turns that into a disk read or write. It'd be extremely slow: on a magnetic disk, each seek takes about 10ms, so you could do about 100 random-access reads and ...
16
It's actually not that hard to design an operating system that doesn't require an MMU. There are a few conveniences you'll have to do without, but nothing insurmountable.
Since different tasks will have to be loaded at different addresses, all your code (except for the kernel, the standard library, and any other code that's part of your base runtime ...
answered Aug 20 '14 at 8:18
Gilles 'SO- stop being evil'
41.3k7 gold badges110 silver badges173 bronze badges
16
In terms of computability, it is known that every modern day computer can be simulated by a Turing Machine whose only storage is a single, linear tape cells that can be written. Assuming you can keep adding unlimited amounts of disk storage, a computer having only hard drives is just as powerful. So certainly you could make a computer without memory.
Of ...
14
As others have already answered, today's common CPUs do not know what a given memory position contains; the software decides.
However, there are other possibilities. Lisp Machines for example used a tagged architecture which stored the type of each memory position; that way the hardware itself could do some of the work of high-level languages.
And even now,...
14
The question is not purely academic. It is a matter of historical record that one of the earliest commercially-produced computers [sorry, I don't recall which offhand] did not have any RAM - all programs were executed by fetching instructions directly off of a magnetic drum [a rotating cylinder with outer surface magnetizable (disks came later)]. It was ...
10
Oblivious RAM is an interface between a program and the physical RAM that when you perform a read or write, does both at the same time on the physical RAM to hide if you are reading or writing. Plus, it shuffles the memory from time to time so that an adversary seeing only accesses to the physical RAM cannot know whetever you accessed the same data twice or ...
9
Forget for a moment all of the issues related to the access to main memory and level 3 cache. From a parallel perspective, ignoring these issues, the program parallelize perfectly when using $p$ processors (or cores), owing to the fact that, once you partition the work to be done through domain decomposition, each core must process either $\left\lfloor {\...
9
No, and not by a long way.
Take 25,000,000 ordinary desktop PCs from 2004. To exceed the supercomputer you're talking about, each would need an 88megaflop CPU, 40Mb of memory and a 940Mb hard disk. In 2004, CPU clock frequencies were already in the GHz range, RAM in the hundreds of megabytes and hard drives in the gigabyte range. And there were many more ...
8
The 8080, as @TEMLIB pointed out, had 16 bit registers (the program counter, the stack pointer and BC, DE, and HL), and could access 216 bytes of memory. The 8080 had an 8-bit bus, and for instructions that required 2 bytes of data or address the bus would be used for 2 cycles.
The 8086 is more interesting. The 8086 had 16 bit registers, but could access ...
7
When you read data from a given memory address, the memory manager checks if there is a copy in the cache. If yes (cache hit), the copy is read into the register. If no (cache miss), the cache is first updated with a row of memory from RAM; then the data can be read into the register.
Conversely, when you write to a memory address, the data is just written ...
7
Byte operations will always be important because a lot of a modern workload involves bytes. Text processing and bytecode interpretation (including emulation of other CPUs) are obvious examples, but also device drivers often need to be able to manipulate bytes efficiently.
Byte-addressed memory can be emulated with word-addressed memory and a reasonable ...
7
No. Disk drives are not Random Addressable like RAM. Instead they're block storage devices. You can't read or write a byte from them. And your CPU cannot read a whole sector at once, they need that random access. Operating systems hide this level of detail from you, but they do so by reading a whole sctor into RAM, modifying it, and writing it back.
As a ...
6
Computers don't use the hexadecimal number system for assembly language. Assembly language, or rather machine code, uses base 256 (typically): instructions are encoded in units of bytes. When displaying machine code, it is customary to use octal or hexadecimal. The reason is that in many cases, the byte is further subdivided into bitstrings, and identifying ...
6
x86 is a 32-bit processor. Memory addresses for x86 are 32 bits. Each byte has a different address, so a 32-bit address means that you can only address up to $2^{32}$ bytes of memory. $2^{32}$ bytes is 4GB. That's why 32-bit processors are limited to 4GB of memory (per application). In particular, each application can use only 4GB of memory. (...
6
Somewhere which is not part of the user accessible memory (i.e. not in the main memory nor in the cache -- that would be too slow, one of the main use of OOO is to hide part of the latency of main memory and low level caches). Probably in register files inside the processor or possibly in the same kind of memory cells used for L1 caches (but not in the L1 ...
6
Cache lines are evicted :
When the OS requests it, it may occur for example in non cache-coherent systems when a peripheral does a DMA transfer (direct transfer from a peripheral to main memory), or if the CPU is shut down to save its state to RAM...
When all the ways of the cache are already used for the requested line.
In a write-through cache, new data ...
6
RAID 2 doesn't use parity: it uses a Hamming code. This allows error correction as well as error detection. Remember that a parity bit is just a bit that tells you whether the sum of the other bits is odd or even. It wouldn't make sense to have more than one of those because they'd all be telling you the same thing.
If you're using RAID 3 with four data ...
6
Free space is a concept at the level of the filesystem, which is part of the operating system. It is up to the filesystem to determine what space is free, and how to exploit it.
Data is stored on the hard drive in a structured way. The filesystem divides the drive into sectors (basic units, usually 512, 1024, 2048, or 4096 bytes), and maintains data ...
6
"In-order" processors only issue instructions in order. Completion is out-of-order even on most processors that are called "in-order". "in-order" just means: if the processor needs to stall the issuing of the next instruction because of a RAW, WAW, or WAR dependence, it can't issue any other instruction during the stall.
In ...
5
Start with a simpler example. Suppose you only had 3 address bits, rather than 24. With $3$ bits we could have $2^3=8$ addresses: 000, 001, 010, 011, 100, 101, 110, 111. In this case, we could think of memory as being divided up into 8 chunks, of equal sizes, with one address per chunk:
memory: chunk 0 | chunk 1 | chunk 2 | chunk 3 | chunk 4 | chunk 5 | ...
5
I decided to try out __builtin_prefetch() myself. I'm posting it here as answer in case others want to test it on their machines. The results are close to what Jukka describes: About a 20% decrease in running time when prefetching 20 elements ahead versus prefetching 0 elements ahead.
Results:
prefetch = 0, time = 1.58000
prefetch = 1, time = 1.47000
...
5
In old computer you actually had a row of switches on the front panel
that would allow entering 1s and 0s directly by hand in the registers
of the machines. But this is no longer done.
You never have 1s and 0s, unless you ask the machine to print its
internal information as a sequence of 1s and 0s. All information is
already in the machine encoded as ...
5
This is a very broad question which would be far easier to answer in person with a whiteboard than in a short online missive.
I found this document for the design of a simple computer from Purdue (part of an engineering program assignment). The document shows the design of an 8 bit computer that would be far simpler to explain than your average CPU of ...
5
Would it make any difference performance-wise to only use the largest variable size on the platform and use business logic to enforce reasonableness in the values being processed and stored?
Yes, it could make your performance worse.
Memory, memory bandwidth, cache density are primary concerns. Larger data size can:
result in increased cache and ...
5
So why do we still use this architecture in the majority of modern
computing?
The assumption itself, first clause: Modern Computer <= Von Neumann
Firstly, do note that the Von Neumann architecture is not used exclusively: almost any current "Von Neumann" machine except for very small microcontrollers (which are occasionally Harvard machines) features ...
5
"32-bit" describes the size of many of the units of data that the processor can use. In this context, it refers to the size of memory addresses. A 32-bit address can address $2^{32}$ distinct objects; in a byte addressable system, that means it can address $2^{32}$ distinct bytes.
We don't give addresses to individual bits in memory, but rather groups of ...
4
DDR3 access is indeed pipelined. http://www.eng.utah.edu/~cs7810/pres/dram-cs7810-protocolx2.pdf slides 20 and 24 show what happens in the memory bus during pipelined read operations.
(partially wrong, see below) Multiple threads are not necessary if the CPU architecture supports cache prefetch. Modern x86 and ARM as well as many other architectures have an ...
Only top voted, non community-wiki answers of a minimum length are eligible