# Tag Info

4

"32-bit" describes the size of many of the units of data that the processor can use. In this context, it refers to the size of memory addresses. A 32-bit address can address $2^{32}$ distinct objects; in a byte addressable system, that means it can address $2^{32}$ distinct bytes. We don't give addresses to individual bits in memory, but rather groups of ...

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It's great that you're curious. A simplified explanation follows with a few links to delve into: All of the programs running in parallel is actually an illusion that is created by the OS. Even if we have a uniprocessor system, the OS can still achieve the same thing. For multiple programs running on the system, OS creates separate processes. Separate ...

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Go to Agner manuals page and download them all, you will find tons of interesting info there. In particular, microarchitecture.pdf says There is a false dependence between memory addresses with the same set and offset, i.e. with a distance that is a multiple of 4 Kbytes: ;Example 9.6. Sandy bridge false memory dependence mov [rsi],eax mov ebx,[rsi+1000H]...

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A buffer is usually used only as temporary storage while something is being transmitted or read. For instance, you might be reading data from a slow-response external storage medium (e.g., a CD) and processing it continuously. In this setting, the first process reads chunks of data from the medium and writes it to the buffer on demand, while the latter reads ...

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Buffer is a concept. It's a structure used to hold data to keep it "closer" while you're processing it. Like buffering a YouTube video. Many types of memories are used as buffers. RAM is certainly great for holding buffers, but for large data you can also buffer data on a hard drive, or an SSD. Buffers are mainly used to hold data that is costly to read ...

2

CPU registers are often counted as part of primary memory (since they are directly accessed by the CPU - see Wikipedia) and are often volatile, so it seems likely that the expected answer is (1). However, this is one of those annoyingly ambiguous questions which depend on the student memorising a very specific set of definitions and ignoring any exceptions.

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No, the author is wrong. I have used 32 bit processors that could address 64 GB of RAM. Memory is restricted by the number of address lines, multiplied by the number of bytes addressed by each individual value of address lines. Address space of one application was limited to 4GB, but you could have a dozen applications running at the same time, each ...

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So why do we still use this architecture in the majority of modern computing? The assumption itself, first clause: Modern Computer <= Von Neumann Firstly, do note that the Von Neumann architecture is not used exclusively: almost any current "Von Neumann" machine except for very small microcontrollers (which are occasionally Harvard machines) features ...

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What you are looking for is named "address decoding". If a processor can address 64kB, its address bus is something like A[15:0]. If you use a 1kB memory chip, its addresses will be A[9:0]. There are several options : Either you don't connect the bits A[15:10] of the processor. The memory will be mirrored at several "places" in the CPU address map, in ...

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There are two different address spaces, let's call them logical and physical. The addresses a programmer thinks about are the logical addresses, the page table translates logical addresses to physical addresses. As you point out, paging allows you to sparsely map the logical address space to the physical address space. But the bold sentences in your quote ...

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You can look at how one of the existing DRAM simulators work. Consider, for example, Ramulator, which is a popular academic DRAM simulator. Ramulator Models main memory as a tree of nodes, where the root node represents a memory channel and lower nodes represent ranks, bank groups (supported in DDR4), banks, rows, and columns. For the DRR4 and DRR3 protocols,...

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Buses usually connect the central processing unit (CPU) with peripheral devices, like memory or other Input/Output devices. To activate a memory you need to do two things: - specify the cell in the memory you want to write to / read from (that would be the address) - give the data to write to the memory, or take the data from the memory (this information ...

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The RAM makes use of direct-memory-access, briefly this means that An element of data or instructions (such as a byte or word) can be directly stored or retrieved by selecting and using the locations on the storage media. Now this can be happened with the use of a DMA controller, which bypasses CPU to transfer data directly between I/O device and ...

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Vladislav is right, but there is more that can be said. A loop means running some code, and then running it again. An if just conditionally branches to two different bits of code. If one of those bits of code can jump back to the earlier code, or to the if itself, then you can get a loop. So you need something that can jump somewhere else. A goto is ...

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The presented timing for first word assumes the row is currently open (i.e., is only CAS latency, in nanoseconds). For random accesses, RAS latency is added; if another row in the bank is still active, PRECHARGE latency (to write back the active row before opening the desired row) is added. RAS and PRECHARGE latencies are typically proportional to CAS ...

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Yes. You can have a smaller memory chip. Trying to read or write an address beyond that range might cause unpredictable behavior or meaningless results, so you'd want to avoid doing that.

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SSD drives are often used as buffers. You wouldn’t call an SSD drive RAM, would you? RAM is Random Access Memory. A buffer is a data structure used to optimise the flow of data. You make a category mistake. You compare things that cannot be compared. It’s like asking why your nose isn’t called Usain Bolt when they are both running.

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The straightforward manner of indexing and tagging a cache is for the index to be the address (in blocks, i.e., removing the block offset) modulo the way size (in blocks) and for the tag to be the quotient of these numbers. The computational cost of exact division for non-powers-of-two makes this less practical for first level caches, but Mersenne number (2n-...

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Performance comparisons are not hardware agnostic because performance does not scale proportionately for all applications across all computers. Even if the relative performance of a particular program is believed to be independent of hardware reasonably likely to be used for the problem the program addresses, providing this information can help when ...

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