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For anyone visiting this thread in the future, FIFO can have less page faults in some scenarios. In this one ( <2, 6, 5, 7, ..., ..., ...> ), it can be completed with 2, 8, 6. The access of 2 means that the least recently used page is 6, but the first page in is still 2. The access of 8 replaces 2 in FIFO, but 6 in LRU. The access of 6, therefore, is ...


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There are few things to be cleared first. Lets assume a away set associative cache with bwide cache-lines and c number of cache lines. In this configuration, size of the cache is a X b X c. Number of bits needed to represent the number of cachelines, is called index bits. (ex: 1024 cachelines will need 10 bits). When we need to load data, the index bits of ...


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