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The cost of a branch misprediction depends on the depth and width of the pipeline and not the amount of code guarded by a condition. A processor keeps fetching and decoding down the wrong path until the branch is resolved and the correct target determined. In a two-wide processor with five stage before branch resolution (a "moderate performance design", say ...


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There are many ways this kind of situation be handled. Clever compilers If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is reading from the memory location 0x12345 and the variable allocated at memory location 0x12345 is not "volatile", compiler will optimize your code so that the next ...


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Many modern processors have predicated instructions, for example the CMOVE (conditional move) on x86 processors, lots of predicated instructions on ARM 32 bits, and a lot fewer instructions on ARM 64 bit. When these instructions are executed, there is no branching at all. For example, a conditional move "move register A to register B if a condition is true"...


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THe answers are correct. There is a data hazard when the information stored in the "regular" location (generally a data reg) is incorrect with respect to the program flow. Here information copied in the ID stage at line 2 will be the previous value of $t1, as the new one will be copied at the end of WB stage of instruction 1 (and hence at the end of MEM ...


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beq doesn't contain the destination address in the instruction, but an offset relative to the location of the instruction. For example "branch if equal to the instruction 12 words ahead of the branch instruction". You cannot execute such an instruction if you don't know what the address of the branch instruction was.


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By using different phases of a clock cycle for register write and register read, the number of register file ports can be reduced. (This can reduce area and latency.) A two-read and one-write instruction would otherwise require three register file ports (or introduce a structural hazard); by using different phases of the cycle one port can be used for both ...


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"Byte addressable" means that a 32-bit address points to a single byte of memory, so if you increment that address, it points one byte further. The opposite is "word addressable", where (on a 32-bit processor) every 32-bit address points to a 32-bit word, so if you increment that address, it points four bytes further in memory. EDIT: As Ran G points out, ...


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Performance improvement is possible because the fetching of the predicted instructions happens at the same time as executing the current instruction. If you guess right, fetching the next instruction was free.


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In simple implementations, byte addressable is more important for writes than for read. Because, with RAM, you read all 32 or 64 bits then steer data with a multiplexer. For writes, you need to be able to selectively update each part. (An alternative, in early DEC Alpha processors, was not to provide any byte wide access instructions, they eventually added ...


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Inserting NOPs is the stall. It delays execution until the result is ready. A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to each functional unit to control how it behaves. Including whether to pull in a new instruction. The decoder checks dependencies between instructions and when ...


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You are absolutely, completely on the wrong path here. Predicated instructions are used to avoid branching. A predicated instruction avoids the cost of a branch plus possible penalty for a mispredicted branch. If you have 100 instructions on the if and the else side, then you would need 200 predicated instructions instead of 100 unpredicated instructions ...


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The computation of instructions per cycles is a measure of the performance of an architecture, and, a basis of comparison all other things being equal.  IPC can be used to compare two designs for the same instruction set architecture, as in the question you're asking comparing two design alternatives for a MIPS architecture. Or, IPC can be used to ...


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First, there is a source of confusion between the table you're showing and the diagram.  The table and diagram both use the term "ALUOp" but for the diagram this is the term for the output of the "Control" going into the "ALU control", whereas for the table this is the term for the output of the "ALU control" going into the ALU! Can't ALUcontrol tell ...


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For certain instructions in certain pipeline stages, we don't care about the results or operation of one or more of the hardware's many functional units. Let's say the processor implementation has several functional units, e.g. in the ALU, for addition/subtraction, one for and/or, one for multiplication, one for division, one for shifting, and maybe even (...


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Learning assembly language will be helpful for you in understanding computer architecture, because the CPU is designed to run the instructions that are part of its assembly language. So, to understand what the CPU is doing and why it was designed that way, you need to know what operations it is designed to support.


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Look at data dependecies: lw $r0, 4($r0) sw $r0, 4($r0) add $r0, $r0, $r0 At line 1, $r0 is being written to. At line 2, $r0 is being read. Therefore we have a RAW hazard, read after write. There is also a WAR hazard between line 2 and 3 because the register is being written after reading it.


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The hazard stems from the fact that the lw instruction updates register \$r0 at the 5th stage of the pipe (write-back) while the sw and the add instructions require the updated data at the 2nd stage of the pipe (decode/read). Putting everything on a single time line (assuming the lw execution begins at time $t=1$), the correct value of \$r0 will be ...


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