5
votes
Are there competitions for integer programming?
There are no competitions targeting general integer programming or mixed integer programming, but there are (or were) benchmarks, such as the MIPLIB (linear) and the MINLPLIB (nonlinear).
There are ...
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5
votes
Accepted
Are there competitions for integer programming?
There are competitions for constraint satisfaction solvers. Some problems there can be readily translated to IP solvers as well. See e.g., MiniZinc challenge which has taken place yearly since 2008 or ...
- 22k
4
votes
Accepted
Do number of registers and width of register have to be the same?
The number of registers and their width is not really related, they just happen to be the same in MIPS-32. You can look at other ISAs for different combinations of register width/number:
IA64: 128 64-...
- 1,813
4
votes
Predication execution
The cost of a branch misprediction depends on the depth and width of the pipeline and not the amount of code guarded by a condition. A processor keeps fetching and decoding down the wrong path until ...
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3
votes
Predication execution
Many modern processors have predicated instructions, for example the CMOVE (conditional move) on x86 processors, lots of predicated instructions on ARM 32 bits, and a lot fewer instructions on ARM 64 ...
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3
votes
CPU pipelining stages
There are many ways this kind of situation be handled.
Clever compilers
If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is ...
- 305
3
votes
Are there competitions for integer programming?
There was a Pseudo-Boolean solver competition from 2005-2012, but (as far as I can tell) nothing since then. Integer Linear Programming is a subset of Pseudo-Boolean programming. See the 2012 ...
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2
votes
In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?
beq doesn't contain the destination address in the instruction, but an offset relative to the location of the instruction. For example "branch if equal to the instruction 12 words ahead of the branch ...
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2
votes
Accepted
Why is the opcode 0 for all r-type instructions? Please explain your answer
In designing an ISA, there are many tradeoffs that can/need to be taken.
This makes it slightly challenging to answer why questions but I will do my best.
In mips I am sure you are aware of the three ...
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2
votes
Accepted
how pseudo direct addressing works?
Pseudo direct addressing is not intended for relative jumps. It is an absolute jump. If you want a relative jump, don't use pseudo direct addressing.
It's not correct that the limit is $2^{28}$ ...
D.W.♦
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2
votes
how pseudo direct addressing works?
In MIPS-speak, these areas of memory of 28 (26+2; the +2 is because instructions are four bytes in size) bit address space (256MB) are referred to as "superblocks". Pseudo-direct addressing allows you ...
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2
votes
Accepted
Data hazard after in load word after addi
THe answers are correct.
There is a data hazard when the information stored in the "regular" location (generally a data reg) is incorrect with respect to the program flow.
Here information copied in ...
- 321
2
votes
MIPS pipeline: MEM stage takes one cycle?
The MEM stage takes one cycle. But the write isn’t completed at that time. It is completed4, 10, 75 or many cycles later.
If you perform another write instruction, the MEM stage may be stalled until ...
- 24.9k
1
vote
Accepted
How can this MIPS processor execute one instruction in one cycle?
The register file in this design is multi-ported, and the read ports work like combinational circuits. The only thing between the read input and the output port is propagation delay. The clock signal ...
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1
vote
Why are lw and sw byte addressable but jump and beq word addressable?
On MIPS, each instruction is exactly one word long, and is byte-aligned to words. Hence it makes no sense to jump to a byte address in the middle of a word, because that can't be the legal start of an ...
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vote
Does higher cpi give better performance?
CPI = cycled per instruction. Higher CPI = more cycles = more time to get the work done. So it’s worse.
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1
vote
Bytes addressable processor
"Byte addressable" means that a 32-bit address points to a single byte of memory, so if you increment that address, it points one byte further.
"Word addressable" means that (on a 32-bit processor) ...
- 6,920
1
vote
Accepted
In instructions pipelining, why does register read/write take up only half clock cycle?
By using different phases of a clock cycle for register write and register read, the number of register file ports can be reduced. (This can reduce area and latency.) A two-read and one-write ...
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1
vote
Data hazard or forward in MIPS SW after LW in this case?
Basically no, but what does happen differs.
Typical educational material doesn't forward into the MEM stage, even though indeed it could do that, and may show a hazard detection unit (which makes the ...
- 1,813
1
vote
Predication execution
Performance improvement is possible because the fetching of the
predicted instructions happens at the same time as executing the
current instruction. If you guess right, fetching the next
...
- 379
1
vote
Byte/word addressing
In simple implementations, byte addressable is more important for writes than for read.
Because, with RAM, you read all 32 or 64 bits then steer data with a multiplexer. For writes, you need to be ...
- 1,756
1
vote
Bubble in a pipeline
Inserting NOPs is the stall. It delays execution until the result is ready.
A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to ...
- 4,078
1
vote
predication, branch prediction question
You are absolutely, completely on the wrong path here.
Predicated instructions are used to avoid branching. A predicated instruction avoids the cost of a branch plus possible penalty for a ...
- 24.9k
1
vote
How do I calculate Instruction Per Clock?
The computation of instructions per cycles is a measure of the performance of an architecture, and, a basis of comparison all other things being equal. IPC can be used to compare two designs for ...
- 451
1
vote
MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion
First, there is a source of confusion between the table you're showing and the diagram. The table and diagram both use the term "ALUOp" but for the diagram this is the term for the output of the ...
- 451
1
vote
MIPS control signal table(R-type add)
For certain instructions in certain pipeline stages, we don't care about the results or operation of one or more of the hardware's many functional units.
Let's say the processor implementation has ...
- 451
1
vote
Computer Organization and Assembly Language Programming
Learning assembly language will be helpful for you in understanding computer architecture, because the CPU is designed to run the instructions that are part of its assembly language. So, to ...
D.W.♦
- 140k
1
vote
lw and sw hazards example MIPS
Look at data dependecies:
lw $r0, 4($r0)
sw $r0, 4($r0)
add $r0, $r0, $r0
At line 1, $r0 is being written to. At line 2, <...
1
vote
lw and sw hazards example MIPS
The hazard stems from the fact that the lw instruction updates register \$r0 at the 5th stage of the pipe (write-back) while the ...
- 20.3k
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