6
votes
Are there competitions for integer programming?
There are no competitions targeting general integer programming or mixed integer programming, but there are (or were) benchmarks, such as the MIPLIB (linear) and the MINLPLIB (nonlinear).
There are ...
- 475
5
votes
Accepted
Do number of registers and width of register have to be the same?
The number of registers and their width is not really related, they just happen to be the same in MIPS-32. You can look at other ISAs for different combinations of register width/number:
IA64: 128 64-...
- 2,018
5
votes
Accepted
Are there competitions for integer programming?
There are competitions for constraint satisfaction solvers. Some problems there can be readily translated to IP solvers as well. See e.g., MiniZinc challenge which has taken place yearly since 2008 or ...
- 22.5k
3
votes
Are there competitions for integer programming?
There was a Pseudo-Boolean solver competition from 2005-2012, but (as far as I can tell) nothing since then. Integer Linear Programming is a subset of Pseudo-Boolean programming. See the 2012 ...
- 8,051
3
votes
Accepted
Why is the opcode 0 for all r-type instructions? Please explain your answer
In designing an ISA, there are many tradeoffs that can/need to be taken.
This makes it slightly challenging to answer why questions but I will do my best.
In mips I am sure you are aware of the three ...
- 619
3
votes
CPU pipelining stages
There are many ways this kind of situation be handled.
Clever compilers
If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is ...
- 325
3
votes
Predication execution
Many modern processors have predicated instructions, for example the CMOVE (conditional move) on x86 processors, lots of predicated instructions on ARM 32 bits, and a lot fewer instructions on ARM 64 ...
- 28.3k
3
votes
R2000 ALU Design
What you're looking for is unlikely to have ever existed.
The R2000 ALU was almost certainly not designed in terms of gates, but either in a high-level synthesis language such as Verilog, or in terms ...
- 21.6k
2
votes
Bubble in a pipeline
Inserting NOPs is the stall. It delays execution until the result is ready.
A simple pipelined CPU will have a instruction decoder that controls the entire CPU at a low level setting control lines to ...
- 4,301
2
votes
In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?
beq doesn't contain the destination address in the instruction, but an offset relative to the location of the instruction. For example "branch if equal to the instruction 12 words ahead of the branch ...
- 28.3k
2
votes
Accepted
how pseudo direct addressing works?
Pseudo direct addressing is not intended for relative jumps. It is an absolute jump. If you want a relative jump, don't use pseudo direct addressing.
It's not correct that the limit is $2^{28}$ ...
D.W.♦
- 156k
2
votes
how pseudo direct addressing works?
In MIPS-speak, these areas of memory of 28 (26+2; the +2 is because instructions are four bytes in size) bit address space (256MB) are referred to as "superblocks". Pseudo-direct addressing allows you ...
- 21.6k
2
votes
Accepted
Data hazard after in load word after addi
THe answers are correct.
There is a data hazard when the information stored in the "regular" location (generally a data reg) is incorrect with respect to the program flow.
Here information copied in ...
- 321
2
votes
Accepted
Why does this branch data hazard happen during the instruction decode stage?
In the MIPS pipeline, for branches and jumps, all of the arithmetic is done in the instruction decode portion of the pipeline. See this MIPS handbook pg. 9, or this handy UCSD ppt. explaining the ...
- 175
2
votes
Are there competitions for integer programming?
It is not really a competition, but there is the well-known Mittelmann benchmark, which lists results for some of the best solvers (including commercial ones) for mixed-integer programming and related ...
- 71
2
votes
MIPS pipeline: MEM stage takes one cycle?
The MEM stage takes one cycle. But the write isn’t completed at that time. It is completed4, 10, 75 or many cycles later.
If you perform another write instruction, the MEM stage may be stalled until ...
- 28.3k
1
vote
Why are lw and sw byte addressable but jump and beq word addressable?
On MIPS, each instruction is exactly one word long, and is byte-aligned to words. Hence it makes no sense to jump to a byte address in the middle of a word, because that can't be the legal start of an ...
- 881
1
vote
Does higher cpi give better performance?
CPI = cycled per instruction. Higher CPI = more cycles = more time to get the work done. So it’s worse.
- 28.3k
1
vote
Bytes addressable processor
"Byte addressable" means that a 32-bit address points to a single byte of memory, so if you increment that address, it points one byte further.
"Word addressable" means that (on a 32-bit processor) ...
- 7,038
1
vote
Detecting Data and Control Hazards for a mips 5 stage pipeline
There are no control dependencies in the code fragment. The non-transitive true (read-after-write) dependencies are:
$i_2\ \delta^f\ i_3$ via register $t_4$
$i_3\ \delta^f\ i_4$ via register $t_0$
$...
- 1,151
1
vote
Data hazard or forward in MIPS SW after LW in this case?
Basically no, but what does happen differs.
Typical educational material doesn't forward into the MEM stage, even though indeed it could do that, and may show a hazard detection unit (which makes the ...
- 2,018
1
vote
Byte/word addressing
In simple implementations, byte addressable is more important for writes than for read.
Because, with RAM, you read all 32 or 64 bits then steer data with a multiplexer. For writes, you need to be ...
- 1,851
1
vote
predication, branch prediction question
You are absolutely, completely on the wrong path here.
Predicated instructions are used to avoid branching. A predicated instruction avoids the cost of a branch plus possible penalty for a ...
- 28.3k
1
vote
Predication execution
Performance improvement is possible because the fetching of the
predicted instructions happens at the same time as executing the
current instruction. If you guess right, fetching the next
...
- 379
1
vote
How do I calculate Instruction Per Clock?
The computation of instructions per cycles is a measure of the performance of an architecture, and, a basis of comparison all other things being equal. IPC can be used to compare two designs for ...
- 451
1
vote
MIPS CPU (Single Cycle MIPS Processor)-R Type instruction ALUOp code confusion
First, there is a source of confusion between the table you're showing and the diagram. The table and diagram both use the term "ALUOp" but for the diagram this is the term for the output of the ...
- 451
1
vote
MIPS control signal table(R-type add)
For certain instructions in certain pipeline stages, we don't care about the results or operation of one or more of the hardware's many functional units.
Let's say the processor implementation has ...
- 451
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