# Tag Info

7

As far as I understand, the difference is indeed the clock/enable. A flip-flop samples the inputs only at a clock event (rising edge, etc.) A Latch samples the inputs continuously whenever it is enabled, that is, only when the enable signal is on. (or otherwise, it would be a wire, not a latch).

7

A flip-flop is implemented as a bi-stable multivibrator; therefore, Q and Q' are guaranteed to be the inverse of each other except for when S=1, R=1, which is not allowed. The excitation table for the SR flip-flop is helpful in understanding what occurs when signals are applied to the inputs. S R Q(t) Q(t+1) ---------------- 0 x 0 0 1 0 ...

2

Here's a big hint, and then I'll let you work out the rest for yourself. Because we want cs.SE to be a collection of questions and answers, please post your solution as an answer. Edge-triggered D flip flops are generally done using the "two RS flip flop" design that you have. You got that right. Reading from left to right, I'm going to call these RS flip ...

2

This feels like a homework question, but I'll at least try to point you in the right direction. The difference between a latch and a flip-flop is that a flip-flop is clocked. At first glance, I thought it was a latch since there was no clock labelled as such, but this might not actually be the case. The clock is an input that will determine when the state ...

1

The notion of a "line" is an abstraction we impose. Currently our memory works as follows: you provide an address to the memory module that you want to read, and it returns the value at that address; or if you want to update memory, you provide an address and the new value, and it overwrites the value at that address with the new value. Why do we ...

1

With the answer I got, and after I searched in Electrical engineering. I think I was both wrong and right. In fact it looks like we "can" use gate on clock signal theoretically, but in practice as Alain Merigot said (don't know how to mention) it can cause some trouble. The problem with gates is that you cannot master their traversal time (that ...

1

Create a FSA that falls on the same state at the end of a 100 sequence. Create a second independent FSA that falls on the same state upon the end of 011 sequence. Now feed a zero to both FSAs at the same time and take note of the pair of states reached. Now go back and feed a 1 and take note of the pair of states reached, and so on. You will end up with a ...

1

You are asking many different questions. The usual rule is one question per post. To help you get started, here is how to compute $S_1 \cap S_{\min S_1}$ (defined as $\emptyset$ if $S_1 = \emptyset$). The input to the circuit is the $n^2$ variables $x_{i,j}$, indicating $i \in S_j$ (this means that they are TRUE if the condition holds, and FALSE if it doesn'...

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