27
votes
Accepted
If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?
The trick to making this work is "paging." When bringing data from a hard disk into physical memory, you don't just bring a few bytes. You bring an entire page. 4k bytes is a very common page size.
...
- 3,359
23
votes
Accepted
Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux
The physical address for the start of a page frame or page table is obtained by taking the 40-bit PPN and appending 12 zero bits. That gives you a 52-bit physical address, which is the start of the ...
D.W.♦
- 164k
11
votes
Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux
Alignment is required for page tables because there's literally nowhere to store the low address bits.
The bottom 12 bits of a page directory entry is flags like present, accessed, user/supervisor, ...
- 1,065
7
votes
Difference between page table and inverted page table
An inverted page table is just a hash map. An inverted page table always fits in DRAM because it is proportional in size to the DRAM.
A DRAM total space is divided into $N$ page frames. If the size ...
- 17.8k
6
votes
Accepted
Where are 'Base & Bounds' registers located?
The values for base and limit must be stored in registers somewhere; it would be highly inefficient to read these from memory on every memory access.
The distinction between "CPU" and "MMU" isn't ...
- 23.1k
6
votes
Accepted
Why does page size affect page table size?
Suppose you have a virtual address space of say $32$ bits. Then the virtual address space for each and every process is fixed and it ranges from the byte $0$ to $2^{32}-1$.
Now the for the ease of ...
- 1,152
5
votes
Transform calculation to memory
There's a line of research that studies how to store sensitive data in the CPU's registers instead of RAM. Here's a seminal paper:
TRESOR Runs Encryption Securely Outside RAM. Tilo Müller, Felix C. ...
D.W.♦
- 164k
5
votes
Accepted
How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?
Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on ...
- 2,073
5
votes
Accepted
Question about Context Switching
What I think is meant by "kernel registers" in this context is any values that are stored in registers within the kernel itself.
Note: In what follows, I'm going to talk about what happens ...
- 23.1k
4
votes
Understanding non-faulting and faulting software prefetches
It's unclear what you mean.
A prefetch is faulting exactly when the actual access to the same data would be faulting.
On the other hand, hardware that allows pre-fetches might not actually ...
- 31.4k
4
votes
Why is data fragmentation not possible on main memory (RAM)?
According to https://lwn.net/Articles/211505/, what you imagine should be done by the OS, is already done:
Since Linux is a virtual memory system, fragmentation normally is not a problem; ...
- 41
4
votes
How many times do we access memory with a TLB?
Many systems use more than one level of page tables, so you may need to access memory more than two times.
With a TLB and assuming you have a cache hit, then you will only need to access memory once ...
- 251
4
votes
What is the difference between a page and thread?
You're looking at very vague descriptions and asking "What's the difference between these things that haven't been described properly?" For a more detailed understanding, you should, well, look for ...
- 82.1k
4
votes
Accepted
Valid bit incoherence between TLB and Page Table
The typical scenario where this kind of incoherence can occur is when the page table has been changed. In this case, an invalid PTE has become valid; perhaps the area of address space has been ...
- 23.1k
4
votes
Accepted
How LRU is used without special hardware?
The Linux kernel uses a (very rough) approximation of LRU, which is the reason why you find mention of LRU, even though it is not the true LRU algorithm. Here is a description taken from the source:
...
- 3,424
4
votes
Accepted
Buddy system allocator and slab allocator in Linux kernel
A modern operating system manages physical memory as page frames. A page frame can be allocated to a user process or for the kernel to use for its own purposes, such as to allocate its own data ...
- 23.1k
4
votes
Accepted
What is the reason or motivation for having 128-bit pointers?
Pointers don't have to be just memory addresses. Pointers with extra information are known as "fat pointers" and have various uses.
A bounds-checked C implementation may use pointers that ...
- 2,202
3
votes
Accepted
Explain Hashed page tables in operating system
Definitions (What's with the symbols?)
In the diagram, we have these guys:
Virtual Page Number (VPN): p, q
Page Frame Number (...
- 46
3
votes
Accepted
Does MMU contain and manage CPU caches?
First the term MMU refers to many different thing (more on later below). For now let's defined MMU as "virtual to physical address translation".
The caches L1 and L2 are always managed in hardware, ...
- 1,181
3
votes
Accepted
What does 'relocation' mean?
Relocation means moving stuff from one place to another. In your case, there is a program which contains some absolute addresses, which make sense if the program is located at a certain address A. If ...
- 278k
3
votes
Accepted
How does malloc(sizeof(char)) work
Quick note, sizeof(char) is defined to be 1. So you can just simplify to malloc(1).
The real answer however is quite boring. ...
- 13.8k
3
votes
Accepted
How to calculate virtual address space from page size, virtual address size and page table entry size?
Since Logical address size is 47 bit, that means logical address space is 2^47 bytes ( assuming system is byte addressable ).
Otherwise in general if the logical address is not given then also it can ...
- 858
3
votes
Accepted
Representing non-contiguous memory regions as a standard vector with O(1) access
A simple approach is to have a one-level lookup table that maps each block of the array to where it is stored. In other words, for a logical array $A[0\dots n-1]$ containing $n$ bytes, we have a ...
D.W.♦
- 164k
3
votes
Accepted
why do we run out of heap space even if we have virtual memory?
Firstly, even the virtual memory does not imply an infinite amount of memory. I have run out virtual memory quite a few times.
Secondly and more commonly, there is a limit on the amount of memory ...
- 39.1k
3
votes
Do the "virtual memory"s mentioned in the 2 articles refer to different things?
That first link is bogus. I can see where they're getting that misconception from, but it's not actually correct.
D.W.♦
- 164k
3
votes
Accepted
Slowdown when accessing data at page boundaries?
Go to Agner manuals page and download them all, you will find tons of interesting info there. In particular, microarchitecture.pdf says
There is a false dependence between memory addresses with ...
- 1,988
3
votes
Accepted
What does this mean: "The compile-time and load-time address-binding methods generate identical logical and physical addresses"?
What your TB says is absolutely correct & the answer is the latter i.e. the second interpretation.
More particularly:
The logical address & the physical address generated in the compile-time ...
- 46
3
votes
Accepted
How does the OS handle multiple stacks in its physical memory?
The point you make at the very end of your question is the right one.
No modern computer has a stack. In hardware terms it turns out to be superfluous, wasteful and useless.
A stack is superfluous ...
- 1,064
3
votes
How does virtual memory work when it need to save data in physical memory into disk?
There are a few options:
if a page is in memory then it cannot be on disk as well, As such there is no duplication and the issue doesn't exist.
there is more than just the MMU's pagetable to hold ...
- 4,646
Only top scored, non community-wiki answers of a minimum length are eligible