27 votes
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If the virtual address space can be larger than the physical address space, how are the address mappings stored in memory?

The trick to making this work is "paging." When bringing data from a hard disk into physical memory, you don't just bring a few bytes. You bring an entire page. 4k bytes is a very common page size. ...
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  • 3,025
23 votes
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Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux

The physical address for the start of a page frame or page table is obtained by taking the 40-bit PPN and appending 12 zero bits. That gives you a 52-bit physical address, which is the start of the ...
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  • 140k
14 votes

Memory ballooning in the OS

Actually, what you've described confuses ballooning and 'same-page-merging'. I'll try to elaborate on the two to make the distinction apparent. Memory ballooning This is a trick to make sure that ...
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  • 410
11 votes

Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux

Alignment is required for page tables because there's literally nowhere to store the low address bits. The bottom 12 bits of a page directory entry is flags like present, accessed, user/supervisor, ...
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9 votes

Clock page replacement algorithm - Already existing pages

I think this example can clarify all your doubts. For example: Assumes main memory is empty at the start page reference sequence is: 3 2 3 0 8 4 2 5 0 9 8 3 2 ...
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8 votes
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Would it be possible to use the cloud for RAM?

Network latency is orders of magnitude too high for a remote server to usefully share its RAM directly, even if you could cobble together a virtualization layer to make it work. However, today's ...
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  • 7,833
8 votes

Clock page replacement algorithm - Already existing pages

If a reference arrives for a page already in memory, then the replacement algorithm doesn't get invoked at all. The clock replacement algorithm is trying to achieve some of the benefits of LRU ...
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7 votes

How are system calls handled in a virtual machine?

There are 3 common strategies to handle this: 1. Hypervisor traps system calls from guest: The hypervisor checks whether the privileged instruction(effectively system call) came from the guest OS ...
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  • 171
6 votes
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Where are 'Base & Bounds' registers located?

The values for base and limit must be stored in registers somewhere; it would be highly inefficient to read these from memory on every memory access. The distinction between "CPU" and "MMU" isn't ...
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6 votes
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Why does page size affect page table size?

Suppose you have a virtual address space of say $32$ bits. Then the virtual address space for each and every process is fixed and it ranges from the byte $0$ to $2^{32}-1$. Now the for the ease of ...
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5 votes
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Why does quicksort work well with virtual memory?

The phrase in Cormen is a bit obscure (and does read a bit quaint). A 1978 paper by Sedgewick "Implementing Quicksort Programs" has a nutshell on this: The hardware feature on modern computers that ...
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  • 1,230
5 votes

Page management in OS kernels

Page frame management is conceptually very simple; all you really need is a linked list. However, there are two main factors which complicate things: DMA. DMA is one of the few things that might need ...
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  • 18.7k
5 votes
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What are logical addresses and where do they actually reside?

Well, this is the entire point of "virtual memory". When your program runs, the OS makes it believe it has all the memory just for itself. That is, addresses 1 to 10,000 (say), are all empty and ...
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  • 20.3k
5 votes
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Understanding non-faulting and faulting software prefetches

A faulting prefetch is one which (as gnasher729's answer notes) generates any translation (e.g., invalid page table entry), permission, or other fault (e.g., ECC failure, data watchpoint match) ...
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5 votes

Transform calculation to memory

There's a line of research that studies how to store sensitive data in the CPU's registers instead of RAM. Here's a seminal paper: TRESOR Runs Encryption Securely Outside RAM. Tilo Müller, Felix C. ...
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  • 140k
5 votes
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How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?

Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on ...
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  • 1,813
4 votes

Why is data fragmentation not possible on main memory (RAM)?

According to https://lwn.net/Articles/211505/, what you imagine should be done by the OS, is already done: Since Linux is a virtual memory system, fragmentation normally is not a problem; ...
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  • 41
4 votes

Difference between virtual memory and job pool

The concept of “job pool” refers to a batch processing system, where jobs are queued to be executed when resources are available. The job pool contains both jobs that are currently executing and jobs ...
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4 votes
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Effect of Copy-On-Write on 2 processes sharing address space

The fork primitive makes a copy of the process. From within the processes, the parent and the child are almost identical; the few differences are the return value ...
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4 votes

How many times do we access memory with a TLB?

Many systems use more than one level of page tables, so you may need to access memory more than two times. With a TLB and assuming you have a cache hit, then you will only need to access memory once ...
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  • 251
4 votes

Understanding non-faulting and faulting software prefetches

It's unclear what you mean. A prefetch is faulting exactly when the actual access to the same data would be faulting. On the other hand, hardware that allows pre-fetches might not actually ...
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  • 24.9k
4 votes

What is the difference between a page and thread?

You're looking at very vague descriptions and asking "What's the difference between these things that haven't been described properly?" For a more detailed understanding, you should, well, look for ...
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4 votes
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Valid bit incoherence between TLB and Page Table

The typical scenario where this kind of incoherence can occur is when the page table has been changed. In this case, an invalid PTE has become valid; perhaps the area of address space has been ...
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  • 18.7k
4 votes
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How LRU is used without special hardware?

The Linux kernel uses a (very rough) approximation of LRU, which is the reason why you find mention of LRU, even though it is not the true LRU algorithm. Here is a description taken from the source: ...
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  • 3,162
3 votes

How does cpu fetch active program data (using virtual address) from storage when there is a page fault?

The CPU knows nothing about swapping. This is performed by the operating system. When a memory access takes place, the MMU consults page tables to find the physical address that is associated to a ...
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3 votes
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Why is the processes address space a continuous block in RAM?

The term virtual memory applies as soon as there is a mapping from logical (process specific) addresses to physical one. The mapping may be as simple as adding a base to the logical address to get ...
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  • 2,994
3 votes
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Virtual Address and Physical Address Space

When we are using Virtual Memory, we are translating from a Virtual Address Space to a Physical Address Space. To understand why it requires $2^{35}$ entries, consider the page size. In order to byte ...
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  • 509
3 votes
Accepted

Number of addresses in a memory region

A megabyte is $2^{20}$ bytes. The factor of $2$ is because we need to count both reads and writes.
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3 votes
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In memory paging, how does the S.O. know where the page is in secondary Memory?

The first thing is that when the page-table entry is invalid you are allowed to use all the other bits in the page-table entry for whatever you want. So, for example, you could use it to store an ...
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3 votes

Page Table Size in a 4 Level Hierarchical Page Table

The virtual addresses must be canonical, the top 16 bits are all copies of the 48th bit. Using a non-canonical address (in the sense of using it as an address) generates a #GP. See also, the manual, ...
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  • 1,813

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