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gilianzz

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12 votes cast

12 Questions

Votes Activity Newest Views

1

5

votes

2

answers

5k

views

Advantage of byte addressable memory over word addressable memory

computer-architecture memory-hardware

May 21 '15 at 1:51 Paul A. Clayton 2,813

2

votes

2

answers

4k

views

Can a Von Neumann CPU be pipelined?

computer-architecture

Mar 6 '15 at 1:44 Fizz 1,230

9

26

votes

1

answer

4k

views

Is a stack overflow detected by hardware or software?

computer-architecture stacks

Feb 22 '15 at 20:17 Gilles 'SO- stop being evil' 40.1k

2

votes

1

answer

792

views

In which pipeline stage are exceptions detected?

computer-architecture

Mar 29 '15 at 1:33 Wandering Logic 16.6k

1

2

votes

1

answer

748

views

What's the difference between a reorder buffer and an instruction window?

computer-architecture

May 2 '15 at 16:13 Wandering Logic 16.6k

1

vote

1

answer

515

views

Branch predictor question

computer-architecture

Feb 21 '15 at 18:19 Wandering Logic 16.6k

1

vote

1

answer

404

views

Loading a word from a byte addressed cache

computer-architecture cpu-cache

Jun 22 '16 at 7:08 nic 206

2

votes

0

answers

369

views

Future register file in computer architecture

computer-architecture

Apr 16 '15 at 11:55 gilianzz 571

3

votes

2

answers

182

views

Clear interrupt instruction in a pipelined CPU

computer-architecture cpu-pipelines

Aug 16 '15 at 18:29 TEMLIB 1,613

2

votes

1

answer

146

views

Flags register in an out-of-order processor

computer-architecture

May 3 '15 at 18:03 Wandering Logic 16.6k

1

1

vote

2

answers

78

views

Can each VLIW sub-instruction execute any instruction?

computer-architecture

Apr 30 '19 at 1:09 Paul A. Clayton 2,813

1

vote

1

answer

55

views

What data size is sent to and read from physical RAM?

computer-architecture

Mar 11 '15 at 22:04 Paul A. Clayton 2,813

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