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Paul A. Clayton
  • Member for 9 years, 6 months
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21 votes
Accepted

A multi-user, multi-processing operating system cannot be implemented on hardware that does not support

10 votes
Accepted

Which architecture do modern computers use?

9 votes
Accepted

What does it mean when a computer runs 'faster'?

8 votes

How does increasing the page size affect the number of page faults?

8 votes

Why is a superscalar processor SIMD?

6 votes

Bloom Filter for 208 million URLs

6 votes
Accepted

When do structural hazards occur in pipelined architectures?

6 votes
Accepted

How to work out physical address corresponding to logical address?

6 votes
Accepted

Why do most books say that a 1 bit branch predictor mispredicts on the first loop iteration?

6 votes
Accepted

What does "fast-forwarding" mean in the context of CPU simulation?

5 votes
Accepted

Understanding non-faulting and faulting software prefetches

5 votes
Accepted

What are the design issue with today's micro processor

5 votes
Accepted

Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

5 votes

What is the difference between LRU implemented for a cache and for page replacement?

4 votes
Accepted

Advantage of byte addressable memory over word addressable memory

4 votes
Accepted

Can a Von Neumann CPU be pipelined?

4 votes
Accepted

What data size is sent to and read from physical RAM?

4 votes

How is a 2-bit predictor better than a 1-bit predictor at determining loop iterations

4 votes
Accepted

Fastest mode of data transfer

4 votes

Processes and Segmentation

4 votes
Accepted

Clear interrupt instruction in a pipelined CPU

4 votes

Predication execution

4 votes
Accepted

How does cache partitioning prevent covert/side-channel attacks?

4 votes

What type of operations are seen the most at the physical disk level — reads or writes? Why?

3 votes
Accepted

What is a sticky bit in computer architecture?

3 votes

What are the disadvantages of having many registers?

3 votes
Accepted

What happens at the decode phase of the instruction cycle?

3 votes

Calculation of effective average instruction execution time in a 2-level paging system

3 votes

Dynamic loading vs. dynamic linking?

3 votes
Accepted

Amdahl's Law and Computer Science