Paul A. Clayton
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Calculating the pipeline speed up in case we have an infinite amount of stages
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2 votes

The cycle time/clock period is equal to the time doing actual work plus the overhead (represented, simplistically, as "pipeline register delay" in this problem). The time doing actual work ...

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Dynamic selection of cache replacement policy
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0 votes

"Adaptive Insertion Policies for High Performance Caching" (PDF) uses set dueling (where a portion of sets are assigned to different policies for tracking) to select insertion as LRU (next victim). ...

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Neural branch predictors linear, classical predictors exponential, in resources?
1 votes

In a classic perceptron-based branch predictor, each static branch has one weight value for each global history bit. Therefore the storage is equal to the number of static branches with entries times ...

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Importance of Frequency vs CAS Latency in memory performance
1 votes

The presented timing for first word assumes the row is currently open (i.e., is only CAS latency, in nanoseconds). For random accesses, RAS latency is added; if another row in the bank is still active,...

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What is a sticky bit in computer architecture?
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3 votes

A sticky overflow bit means that the next operation that does not overflow (but would set the bit if it did) will not clear the bit. The value is sticky/persistent and must be cleared to detect newer ...

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Confusion in speed up calculation for pipeline architecture
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1 votes

Approach I is calculating the cycles per instruction change independent of frequency increase (presumably the unpipelined design has some hazards that are not present in the pipelined design forcing ...

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In instructions pipelining, why does register read/write take up only half clock cycle?
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1 votes

By using different phases of a clock cycle for register write and register read, the number of register file ports can be reduced. (This can reduce area and latency.) A two-read and one-write ...

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What type of operations are seen the most at the physical disk level — reads or writes? Why?
4 votes

The proportion of reads to writes would be workload and system dependent. Before filtering by caching, reads will typically be more common, if for no other reason than code being read-only and data ...

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Which is faster operations on register operands or immediate operands?
1 votes

The relative performance of instructions using different operand types is somewhat dependent on the instruction set, the processor design, the code being executed, and even the execution environment. ...

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How can a CPU access more memory locations than 2^wordsize?
1 votes

The size of addressable memory is not limited by the size of the memory data bus, the size of instructions, the size of arithmetic operands (e.g., register size), or even the size of addresses used by ...

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Why we need to read memory on a write-miss?
1 votes

There are several issues involved in this design decision. Since conventional DRAM does not support finer-grained write enable (graphics memories often do), when the data was eventually written back ...

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Is there a CPU architecture which allows early register access?
1 votes

Classic VLIW architectures provide this feature. Operations are statically scheduled with fixed latency and the old value would be associated with a register name until an overwriting operation ...

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What are the disadvantages of having many registers?
2 votes

As noted in the question, increasing the number of registers tends to increase instruction size (clustering, functional specialization, windowing, and other features can reduce the encoding overhead ...

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Can CPU's 'shortcut' adding 0, multiplying by 1, and multiplying by 0?
1 votes

In general, processors do not detect and special case identity elements (zero addends, zero shifts, one multiplicants, one divisors) or zero multiplicands. Addition is typically extremely ...

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Pros and Cons of Average Memory Access Time When Increasing Cache Block Size
2 votes

Advantages The advantages of larger block size include: smaller tag storage (or larger cache capacity for a given tag storage budget), greater bandwidth efficiency, memory error correction code ...

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How can i compute tag-index-displacement bits of an address if cache size is not a power of two?
1 votes

The straightforward manner of indexing and tagging a cache is for the index to be the address (in blocks, i.e., removing the block offset) modulo the way size (in blocks) and for the tag to be the ...

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What are some "easy" unreasonable implications of O(1) time memory access?
1 votes

The easiest unreasonable implication is that such ignores the impact of temporal and spatial locality of reference in conventional systems. Processor caches cause accesses to other addresses within a ...

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use of unconditional transfer of control instruction
1 votes

As David Richerby's answer notes, the most common use is for implementing if-then-else, where the unconditional jump hops over the else code. A related use is when the compiler knows conditional code ...

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Can each VLIW sub-instruction execute any instruction?
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As TEMLIB's answer indicates, VLIWs generally limit what operations can be encoded into each slot of the instruction word. The primary constraint is actually structural hazards. The area and power ...

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Are hardware specs relevant in software performance comparisons?
1 votes

Performance comparisons are not hardware agnostic because performance does not scale proportionately for all applications across all computers. Even if the relative performance of a particular ...

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Is automatic multicore support at the hardware or compiler level possible?
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Automatic parallelization of software (at the source code level down to the hardware level) has been actively researched and in some areas has achieved significant speed-ups. This effort can roughly ...

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Why do we have to trade abstraction for speed?
1 votes

By its nature abstraction reduces the communcation of information, both to the programmer and to the lower layers of the system (the compiler, libraries, and runtime system). In favor of abstraction, ...

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What happens if the associativity level is greater than the cache size?
1 votes

Since the associativity is equal to the number of cache blocks in a set, in a traditional cache design there is no sensible interpretation of having associativity greater than capacity; a set cannot ...

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Why would anyone want CISC?
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There are many reasons one would choose to implement a CISC. The most prominent reason is for binary compatibility with an existing CISC instruction set. While software binary translation technology ...

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What happens at the decode phase of the instruction cycle?
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3 votes

Addressing the core of your question, instructions are typically stored in a format that requires some translation (decoding) to become the control signals for instruction execution. Requiring some ...

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On a semiconductor chip, what state (on/off or read/write) corresponds to conducting or insulating behavior?
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In general it is conventional to use high voltage for true/one and low voltage for false/zero. In fact, a notation with the signal name overscored ($\overline{SIGNAL}$) is used to indicate active-low (...

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What uses have been proposed for overlaid skewed associativity?
1 votes

The following possible uses come to mind, though I am not aware of any academic exploration of these ideas. Way Dueling One possible use is to extend the range of set-dueling. Presented in Moinuddin K....

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What does it mean " The outer level page table need not be page aligned?
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2 votes

Having different subtable sizes for different levels of a multilevel page table just means that a different number of bits from the virtual address will be used. The size of each level's subtable is ...

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How does cache partitioning prevent covert/side-channel attacks?
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4 votes

Most L2 (and L3) caches are indexed with the physical (not virtual) address modulo a power of two that is larger than the page size. This allows different physical address colors to map to different ...

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Predication execution
4 votes

The cost of a branch misprediction depends on the depth and width of the pipeline and not the amount of code guarded by a condition. A processor keeps fetching and decoding down the wrong path until ...

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